s1r72801 Epson Electronics America, Inc., s1r72801 Datasheet
s1r72801
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s1r72801 Summary of contents
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... MF1385 - 04 IEEE1394 Controller S1R72801F00A Technical Manual ...
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NOTICE No parts of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson ...
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... For further information, please contact Epson sales representative. Configuration of product number DEVICES S1 R 72801 Comparison table between new and previous number Previous number New number SPC7281F S1R72801F00A 0A E0C33000 S1C33000 F 00A1 00 Packing specification Specifications Shape (F:QFP) Model number ...
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DESCRIPTION .................................................................................................................................................. 1 2. FEATURES ........................................................................................................................................................ 1 3. INTERNAL BLOCK DESCRIPTION .................................................................................................................. 3 3.1 BLOCK DIAGRAM ..................................................................................................................................... 3 3.2 BLOCK DIAGRAM DESCRIPTION ............................................................................................................ 3 4. INTERNAL CONNECTION DIAGRAM .............................................................................................................. 4 5. PIN ASSIGNMENT DIAGRAM .......................................................................................................................... 5 6. PIN DESCRIPTION ...
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... DESCRIPTION The S1R72801F00A is a LINK/Transaction controller based on the IEEE Std. 1394-1955, P1394a Draft 2.0. It integrates a built-in CPU and Flash ROM, and also integrates a part of transaction functions into hardware. If you set a PageTable address and its size, it can automatically fetch subsequent PageTables and transmit data ...
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... S1R72801F00A Built-in CPU Integration of a CPU eliminated the necessity of an external CPU to control this IC. CPU core: 32-bit RISC CPU S1C33000 Harvard architecture (Concurrency of a fetch and load/store) High speed/high performance: Ready for operation with 50MHz Command set: 16-bit fixed length, 105 types of basic ...
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... SIO (serial interface), input and I/O ports, and CTM (clock timer). Internal RAM Block SRAM for the built-in memory area (Area 0). Internal Flash Block Flash for the built-in memory area (Area 10). EPSON S1R72801F00A 1394 1394 LINK & TRAN PHY/LINK Core I/F Register for LINK& ...
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... S1R72801F00A 4. INTERNAL CONNECTION DIAGRAM XRESET U_AD<23:0> AD<23:00> U_DT<15:0> xCSREG<XCE4> xCSBUF<XCE7> DT<15:00> xCSFREG<XCE5> xCSFLS<XCE10> XCE10EX XCE9 XCE8 xINT(K65) XCE6 SLEEP(P33) XRD XWRL XWRH C33 Core BCLK XNMI X2SPDX ICEMD DSIO OSC3 OSC4 PLLC PLLS1 PLLS0 EA10MD2 EA10MD1 EA10MD0 4 U_AD<12:0> U_DT<7:0> ...
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... SS P10 174 DSIO 175 HV 176 DD XNMI 177 XRESET 178 ICEMD 179 INDEX V 180 SS HCLK 181 BCLK 182 N.C. 183 V 184 SS EPSON S1R72801F00A TOP View EPSON S1R72801F00A N.C. 90 XHRST 89 HDD7 88 HDD8 87 HDD6 86 HDD9 85 HDD5 84 HDD10 HDD4 81 HDD11 80 HDD3 79 HDD12 78 ...
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... S1R72801F00A 6. PIN DESCRIPTION Control signals with an “X” as the first character of a pin name are low active. (Excluding X2SPD) Pin Name PIN I/O Reset 1394PHY interface ( Hi-Z (MSB Hi-Z D5 100 B Hi-Z D4 101 B Hi-Z Data Bus with PHY D3 102 B Hi-Z D2 104 B Hi-Z D1 ...
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... DT8 12 B Hi-Z CPU Data Buss DT7 11 B Hi-Z DT6 10 B Hi-Z DT5 9 B Hi-Z DT4 8 B Hi-Z DT3 7 B Hi-Z DT2 6 B Hi-Z DT1 4 B Hi-Z DT0 3 B Hi-Z (LSB) Pin Function IDE DASP Signal (MSB) CPU Address Bus (LSB) EPSON S1R72801F00A Remarks Drive Ability 3mA Drive Ability 6mA 7 ...
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... S1R72801F00A Pin Name PIN I/O Reset C33 External Interface (HV P07 154 B P06 153 B P05 152 B P04 151 B SRDY(P03) 150 B SCLK(P02) 149 B SOUT(P01) 147 B SIN(P00) 146 B K67 144 I K66 143 I P23 142 B P22 141 B P21 136 B P20 135 B XCE10_EX 134 O XCE9 133 O XCE6 ...
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... Pins) GND 148,157,159,170,173,180,184 13,29,46,57,75,92,112,116,117, 118,119,138 (19 Pins) 2,45,48,91,94,137,140,183 (8 Pins) P_EA10M0 Function 1 Built-in Flash Boot Mode 1 External ROM Mode EPSON S1R72801F00A Remarks Pull Down Resistor Integrated Connect to HV when it is mounted. DD Schmitt Input (Bus Holder) Pull Down Resistor Integrated Pull Down Resistor Integrated 9 ...
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... S1R72801F00A 7. FUNCTIONAL DESCRIPTION 7.1 MEMORY MAP 7.1.1 All Memory Space Area Address Area 0 0x000000 0x002000 Area 1 0x030000 0x040000 0x050000 Area 2 0x060000 Area 3 0x080000 Area 4 0x100000 0x100080 Area 5 0x200000 0x200008 Area 6 0x300000 Area 7 0x400000 0x402000 Area 8 0x600000 Area 9 0x800000 Area 10 0xC00000 0xC10000 0xFFFFFF 10 CPU-integrated RAM (8KB) ...
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... controlled by hardware.) • By controlling the above functions from the TRAN & SBP2 Control Block, a PageTable fetch and data transfer according to SBP-2 are executable by hardware. EPSON S1R72801F00A (RxHeaderAreaStart) RxORBAreaStart TxHeaderAreaStart (TxHeaderAreaStart + 0x0040) TxStreamAreaStart IDE – > 1394 DMA Area ...
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... S1R72801F00A 7.2 IEEE1394 PACKET FORMAT 7.2.1 Transmit Packet Format (1) TxAsyncronousePacket <3> QuadReadReq, WriteResp b. – 1 DestinationID QuadReadReq (tcode : 0x4) 1 DestinationID 2 2 WriteResp (tcode : 0x2) 1 DestinationID 2 (2) TxAsyncronousePacket <4> QuadWriteReq, QuadReadResp, BlockReadReq b. – 1 DestinationID QuadWriteReq (tcode : 0x0) 1 DestinationID QuadReadResp ...
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... Description Speed Code 3'b000 3'b001 3'b010 All Other Value Souce Bus ID Description Received AckCode 4'h1 4'h2 4'h4 4'h5 4'h6 4'hB 4'hC 4'hD 4'hE 4'hF All Other Value EPSON S1R72801F00A tcode ExtendedTcode ACK 8 7 tcode (0xE) reserved 8 7 channel tcode (0xA) sy reserved S100 S200 S400 Reserved 0:3FFh, 1:Source ID ...
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... S1R72801F00A 7.2.2 Receive Packet Format (1) RxAsyncronousePacket <4> QuadReadReq, WriteResp b. – 0 DestinationID 1 2 SourceID QuadReadReq (tcode : 0x4) 2 SourceID 3 2 WriteResp (tcode : 0x2) 2 SourceID 3 (2) RxAsyncronousePacket <5> QuadWriteReq, QuadReadResp, BlockReadReq b. – DestinationID 2 SourceID (tcode : 0x0) 1 QuadWriteReq 2 SourceID 3 4 (tcode : 0x6) ...
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... PacketTypeSpecInfo *DataPointer reserved (MSB) DestinationOffset rcode reserved 16 15 – reserved PhyPacket reserved 16 15 – reserved *DataPointer reserved EPSON S1R72801F00A ACK rt tcode pri ExtendedTcode 8 7 b.0 – ACK tcode (0xE) reserved – ...
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... S1R72801F00A (6) RxIsocronousePacket (tcode : 0xA) b. – 1 DataLength Receive Packet Common Format b. – Name Bit count speed ACK 4 PSTS 4 (Note 1) Refer to the Transmit Packet Common spd (speed code). (Note 2) Refer to the Transmit Packet Common Ack (AckCode). ...
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... TECHNICAL MANUAL (and E0C33 Family ASIC Macro Manual). In the built-in CPU core, however, a DMA controller and A/D converter are not integrated; this part is different from the description on the DMA controller and A/D converter given in TECHNICAL MANUAL (and Macro Manual). A low speed oscillation circuit (OSC1) is not available. EPSON S1R72801F00A 17 ...
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... S1R72801F00A 7.6 FLASH CONTROLLER This IC is provided with a function to perform Erase and Write to the Flash ROM. (1) Chip Erase According to a specified sequence, you can erase all memory cells in the built-in Flash ROM to put them in “1” status. After erasing the chip, check that the data of all memory cells is “ ...
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... ISO Async Stream Channel Index Register R/W ISO Async Stream Channel Window Register R/W Compare Offset Address Index Register R/W Compare Offset Address Window Register R/W Cycle Time Register EPSON S1R72801F00A Relation Higher Rank Lower Rank Higher Rank Lower Rank Higher Rank Lower Rank Middle Rank Lower Rank ...
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... S1R72801F00A Address Register Name 0x2D CYCLE_TIME_MH 0x2E CYCLE_TIME_ML 0x2F CYCLE_TIME_L 0x30 HwSBP2Ctl 0x31 HwSBP2Stat 0x32 HwSBP2IntStat 0x33 HwSBP2Index 0x34 HwSBP2Window_H 0x35 HwSBP2Window_L 0x36 PayloadSize_H 0x37 PayloadSize_L 0x38 PageTableSize_H 0x39 PageTableSize_L 0x3A PageTableAdrs0 0x3B PageTableAdrs1 0x3C PageTableAdrs2 0x3D PaqeTableAdrs3 0x3E PageTableAdrs4 0x3F ...
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... IDE Command Control Register R/W IDE Command Control Register R/W IDE Command Control Register R/W IDE Command Control Register R/W IDE Command Control Register R/W IDE Command Control Register R/W IDE Command Control Register R/W IDE Command Control Register EPSON S1R72801F00A Relation Higher Rank Lower Rank Higher Rank Lower Rank 21 ...
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... S1R72801F00A 8.1.2 Register/Bit Table The base address of this register is 0x100000. Address Register Name bit7 0x00 MainIntStat SubIntStat 0x01 SubIntStat SelfIDdone 0x02 (Reserved) 0x03 DmaIntStat 0x04 LinkIntStat1 0x05 LinkIntStat0 UnExpCh 0x06 PhyIntStat SubGap 0x07 (Reserved) 0x08 MainIntEnb EnSubIntStat EnTxIsoCmp EnRxDmaCmp EnTxAsyCmp EnHwSBP2Cm EnIDE_DmaC EnIDE_INTRQ EnBusReset ...
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... IDE_TxStreamPtr[7:2] RxORBClr RxHdrClr TxPayldRdy RxHdrRemain RxORBFull BlkWrAreaSel AsyFIFOEpty SelTxPtr IsoFIFOEpty RxFIFOEpty Memory Map Area Window BusResetORBPointer[7:2] E_Dcrc No_Pkt F_Ack Ack[7:0] EPSON S1R72801F00A bit3 bit2 bit1 bit0 PTaskExec StTaskExec TranExec RxNotRespCm RxBroadCast RxAckDataErr HwSBP2 Index (LSB) (LSB) (LSB) (LSB) LinkRxHdrPtr[12:8] LinkORBPointer[12:8] LinkRxStreamPtr[12:8] ...
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... S1R72801F00A Address Register Name bit7 0x60 IDE_Config0 UltraDmaMode DmaMode 0x61 IDE_Config1 IDE_Reset 0x62 IDE_RegAccCyc 0x63 IDE_PioDmaCyc 0x64 IDE_UltraDmaCyc 0x65 IDE_DmaCtl 0x66 IDE_BusStat DMARQ 0x67 IDE_DmaStat 0x68 IDE_ByteCount0 (MSB) 0x69 IDE_ByteCount1 0x6A IDE_ByteCount2 0x6B IDE_ByteCount3 0x6C IDE_CRC0 (MSB) 0x6D IDE_CRC1 0x6E IDE_TestIndex ...
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... Page Element Remain Length (Bytes) Destination_ID Value Second[2:0] Cycle Count[7:0] bit6 bit5 bit4 (MSB) RxORBAreaStart[7:2] (MSB) TxHdrAreaStart[7:2] (MSB) TxStreamAreaStart[7:2] (MSB) TxStreamAreaEnd[7:2] (MSB) RxStreamAreaStart[7:2] EPSON S1R72801F00A bit3 bit2 bit1 bit0 (LSB) bit3 bit2 bit1 bit0 PageBoundary[2:0] PageElementNumber[4:0] (LSB) SpeedCode[2:0] MaxPayload[3:0] (LSB) Cycle Count[12:8] bit3 ...
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... S1R72801F00A 8.1.3 Register Map (The base address of this register is 0x100000.) Address Register Name Bit Symbol 0x00 MainIntStat 7:SubIntStat 6: TxIsoCmp 5: RxDmaCmp 4: TxAsyCmp 3: HwSBP2Cmp 2: IDE_DmaCmp 1: IDE_INTRQ 0: BusReset 0x01 SubIntStat 7: SelfIDdone 6: SelfIDerr 5: HwSBP2Err 4: HwSBP2BRst 3: LinkIntStat1 2: LinkIntStat0 UltraDmaMode 1: PhyIntStat 0: DmaIntStat 0x02 (Reserved ...
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... R/W 0: Disable 1: Enable R/W 0: Disable 1: Enable R/W 0: Disable 1: Enable EPSON S1R72801F00A H.Rst S.Rst B.Rst 0x00 0x00 – 0x00 0x00 – 0x00 0x00 – 0x00 0x00 – 0x00 0x00 – 0x00 0x00 – 0x00 0x00 – 0x00 0x00 – ...
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... S1R72801F00A Address Register Name Bit Symbol 0x10 ChipCtl 7: Suspend IDE_MdlRst 1: SendTardy 0: SoftReset 0x11 HW_Revision 7: HW_Revision[7] 6: HW_Revision[6] 5: HW_Revision[5] 4: HW_Revision[4] 3: HW_Revision[3] 2: HW_Revision[2] UltraDmaMode 1: HW_Revision[1] 0: HW_Revision[0] 0x12 (Reserved 0x13 (Reserved 0x14 (Reserved ...
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... Max Retry Count Value If maxRty == 0, Single Phase Retry is ignore R 0: Exist IRM Node 1: None IRM Node R(W) 0: Other Node 1: Self Node Physical ID of IRM Node R No exist IRM Node then IRMID= 0x3F EPSON S1R72801F00A H.Rst S.Rst B.Rst 0x00 0x00 – – – 0 – 0x00 0 – ...
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... S1R72801F00A Address Register Name Bit Symbol 0x20 NODE_IDS_H 7: BusID[9] 6: BusID[8] 5: BusID[7] 4: BusID[6] 3: BusID[5] 2: BusID[4] 1: BusID[3] 0: BusID[2] 0x21 NODE_IDS_L 7: BusID[1] 6: BusID[0] 5: PhyID[5] 4: PhyID[4] 3: PhyID[3] 2: PhyID[2] UltraDmaMode 1: PhyID[1] 0: PhyID[0] 0x22 (Reserved 0x23 (Reserved 0x24 PhyAccCtl_H 7: RdReq 6: WrReq ...
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... R/W ISO (Async Stream) Channel Index R/W ISO (Async Stream) Cahnnel Window R/W Compare Address Index R/W Compare Address Window R/W CYCLE_TIME.second_count R/W CYCLE_TIME.cycle_count R/W CYCLE_TIME.cycle_offset EPSON S1R72801F00A Description H.Rst S.Rst B.Rst 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 – ...
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... S1R72801F00A Address Register Name 0x30 HwSBP2Ctl 7: PtNotPresent 6: HOSTtoDev 5: FromStream 4: 3: HwSBP2Rst 2: HwSBP2Rsum 1: HwSBP2Pause 0: HwSBP2Start 0x31 HwSBP2Stat 7: FwPause 6: ErrPause 5: 4: WaitPLReady 3: HwSBP2Exec 2: PTaskExec UltraDmaMode 1: StTaskExec 0: TranExec 0x32 HwSBP2IntStat 7: SplitTimeOut 6: TxAckedIllegal 5: TxAckMiss 4: BrAbort 3: 2: RxNotRespCmp 1: RxBroadCast 0: RxAckDataErr 0x33 HwSBP2Index HwSBP2 Index[3] ...
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... Write:Set PageElement *8 (bytes) Read :Indicate Page Table Size } else { Write:Set Data Length (bytes) Read :Indicate Create PageElement *8 (bytes) } R/W Write: Set PageTable Offset Address Read: Indicate NextPageTable Offset Address EPSON S1R72801F00A H.Rst S.Rst B.Rst 0x00 0x00 – 0x00 0x00 – 0x00 0x00 – ...
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... S1R72801F00A Address Register Name Bit Symbol 0x40 LinkRxHdrPtr_H LRHP[12] 3: LRHP[11] 2: LRHP[10] 1: LRHP[9] 0: LRHP[8] 0x41 LinkRxHdrPtr_L 7: LRHP[7] 6: LRHP[6] 5: LRHP[ UltraDmaMode 1: 0: 0x42 LinkRxORBPtr_H POP[12] 3: POP[11] 2: POP[10] 1: POP[9] 0: POP[8] 0x43 LinkRxORBPtr_L 7: POP[7] 6: POP[6] 5: POP[5] 4: POP[4] 3: POP[3] 2: POP[ ...
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... Received Packet Stream Data Area IDE Pointer Write is ignore Read is always zero Write is ignore Read is always zero R/W Transmit Packet Stream Data Area IDE Pointer Write is ignore Read is always zero EPSON S1R72801F00A H.Rst S.Rst B.Rst 0x00 0x00 – 0x00 0x00 – 0x00 0x00 – ...
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... S1R72801F00A Address Register Name Bit Symbol 0x50 BufControl 7: TxStreamClr 6: RxStreamClr 5: RxORBClr 4: RxHdrClr UpdLinkTxStrm 0x51 BufMonitor 7: RxPayldRdy 6: TxPayldRdy RxHdrRemain 2: RxORBFull UltraDmaMode 1: RxStreamFull 0: RxHdrFull 0x52 AsyDmaCtl 7: AsyChnlSel BlkWrAreaSel 3: AsyFIFOEpty 2: AsyFIFOClr 1: AsyTxMon 0: AsyStart 0x53 IsoDmaCtl 7: IsoChnlSel SelTxPtr 3: IsoFIFOEpty 2: IsoFIFOClr ...
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... Add Header CRC Error R Add Data CRC Error R Transmit Next Packet R Optional AckCode R Transmit AckPacket R/W Optional AckCode EPSON S1R72801F00A H.Rst S.Rst B.Rst 0x00 0x00 – 0x00 0x00 – 0x00 0x00 – 0x00 0x00 – 0x00 0x00 – ...
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... S1R72801F00A Address Register Name Bit Symbol 0x60 IDE_Config0 7: UltraDmaMode 6: DmaMode 5: ActPort 4: IDE_Slave 3: DMARQ_Level 2: Swap 1: 0: 0x61 IDE_Config1 7: IDE_Reset UltraDmaMode 1: 0: R/W 0x62 IDE_RegAccCyc 7: Assert Pulse[3] 6: Assert Pulse[2] R/W IDE Register Access Strobe Signal Assert Pulse 5: Assert Pulse[1] 4: Assert Pulse[0] 3: Negate Pulse[3] ...
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... EPSON S1R72801F00A H.Rst S.Rst B.Rst 0x00 0x00 – 0x00 0x00 – 0x00 0x00 – 0x00 0x00 – 0x00 0x00 – 0x00 0x00 – 0x00 0x00 – 0x00 0x00 – ...
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... S1R72801F00A Address Register Name Bit Symbol 0x70 IDE_CS00 0x71 IDE_CS01 UltraDmaMode 1: 0: 0x72 IDE_CS02 0x73 IDE_CS03 0x74 IDE_CS04 0x75 IDE_CS05 ...
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... R/W Read : Data Bus Hi – Impedance Write: Not Used Control Block Register R/W Read : Alternate Status Write: Device Control Control Block Register R/W Read : (obsolete) Write: Not Used EPSON S1R72801F00A H.Rst S.Rst B.Rst 0x00 0x00 – 0x00 0x00 – 0x00 0x00 – 0x00 0x00 – ...
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... S1R72801F00A 8.1.4 Detail Description of Register (The base address of this register is 0x100000.) Address Register Name Bit Symbol 0x00 MainIntStat 7:SubIntStat 6: TxIsoCmp 5: RxDmaCmp 4: TxAsyCmp 3: HwSBP2Cmp R(W) 0: None 2: IDE_DmaCmp R(W) 0: None 1: IDE_INTRQ 0: BusReset Main Interrupt Status Register When this IC interrupts the CPU, the CPU first reads this register to handle it, indicating which Interrupt Status Register is a factor of this interrupt ...
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... BusReset in process HwSBP R(W) 0: None 1: Link1 Interrupt Occurred R(W) 0: None 1: Link0 Interrupt Occurred R(W) 0: None 1: PHY Interrupt Occurred R(W) 0: None 1: Dma Interrupt Occurred R/W Description EPSON S1R72801F00A H.Rst S.Rst B.Rst 0x00 0x00 – H.Rst S.Rst B.Rst 0x00 0x00 – 43 ...
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... S1R72801F00A Address Register Name Bit Symbol 0x03 DmaIntStat 7: 6: TxAsyRtyGo 5: TxAsyBCSent R(W) 0: None 4: RxDmaFaild 3: TxAsyFaild 2: TxIsoFaild 1: TxAsyBRAbort R(W) 0: None 0: TxAsyMiss DMA Interrupt Status Register The value of each bit of this register indicates the status of a corresponding interrupt source. If these bits become “H” when the associated bit of the DMAIntEnb Register is “1”, this register asserts the interrupt signal to the CPU ...
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... MaxRetry Register is not 0 and this bit becomes “1”. R/W Description R(W) 0: None 1: Ack_tardy Sent R(W) 0: None 1: Rx Packet Header CRC Err R(W) 0: None 1: Rx Packet Tcode Unknown R(W) 0: None 1: Tx Retry Exceeded EPSON S1R72801F00A H.Rst S.Rst B.Rst 0x00 0x00 – 45 ...
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... S1R72801F00A Address Register Name Bit Symbol 0x05 LinkIntStat0 7: UnExpCh 6: DupliCh 5: IsoArbFaild 4: CycTooLong 3: CycOverFlw 2: CycEvent 1: CycLost 0: CycArbFail LINK Core Interrupt Status Register 0 The value of each bit of this register indicates the status of a corresponding interrupt source. If these bits become “1” when the associated bit of the LINKIntEnb0 Register is “1”, this register asserts the interrupt signal to the CPU ...
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... ArbtrationResetGapDetected R(W) 0: None 1: PHY Interrupt Detected R(W) 0: None 1: PHY Register Write Done R(W) 0: None 1: PHY Register Read Done R/W Description EPSON S1R72801F00A H.Rst S.Rst B.Rst 0x00 0x00 – H.Rst S.Rst B.Rst 0x00 0x00 – 47 ...
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... S1R72801F00A Address Register Name Bit Symbol 0x08 MainIntEnb 7: EnSubIntStat 6: EnTxIsoCmp 5: EnRxDmaCmp 4: EnTxAsyCmp 3: EnHwSBP2Cmp 2: EnIDE_DmaCmp R/W 1: EnIDE_INTRQ 0: EnBusReset Main Interrupt Enable Flag Register This register enables/disables an interrupt factor of the MainIntStat Register. Setting the corresponding bit to “1” enables an interrupt to the CPU. Address Register Name ...
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... R/W 0: Disable R/W 0: Disable R/W 0: Disable R/W 0: Disable Bit Symbol R/W R/W 0: Disable R/W 0: Disable R/W 0: Disable R/W 0: Disable R/W 0: Disable R/W 0: Disable R/W 0: Disable R/W 0: Disable EPSON S1R72801F00A Description H.Rst S.Rst B.Rst 1: 1: Enable 1: Enable 1: Enable 0x00 0x00 1: Enable 1: Enable 1: Enable 1: Enable Description H.Rst S.Rst B.Rst 0x00 0x00 1: Enable ...
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... S1R72801F00A Address Register Name Bit Symbol 0x0E PhyIntEnb 7: EnSubGap 6: EnArbGap EnPhy_int 1: EnPhyWrDone 0: EnPhyRdDone PHY Core Interrupt Enable Flag Register This register enables/disables an interrupt factor of the PHYIntStat Register. Setting the corresponding bit to “1” enables an interrupt to the CPU. Address Register Name ...
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... Enable Posted WB 0: Disable Poosted WQ 1: Enable Posted WQ 0: PHY 1394.a uncorrespond 1: PHY 1394.a correspond 0: Ack Acceleration Disable 1: Ack Acceleration Enable 0: Cycle Master Not Capabl 1: Cycle Master Capable EPSON S1R72801F00A H.Rst S.Rst B.Rst 0x03 0x03 0x03 H.Rst S.Rst B.Rst 0x00 0x00 – ...
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... S1R72801F00A Address Register Name Bit Symbol 0x19 LinkCtl_L 7: EnLink 6: 5: PLIFrst 4: IgnrBChdr 3: IgnrBCdata 2: RxBusyMode 1: DualRtyEnb 0: SinglRtyEnb LINK Core Control Register Lower Rank This register controls the functions of the LINK core. Bit7 Enable LINK Controls whether communications with other nodes are enabled. ...
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... Description R/W Maximum Number of certain Priority Arb Request R/W Description Dual Phase Retry Limit R/W Second Limit R/W Cycle Limit If (SecLimit == 0 and CycLimit==0) Dual Phase is ignore EPSON S1R72801F00A H.Rst S.Rst B.Rst 0x00 0x00 0x00 H.Rst S.Rst B.Rst 0x00 0x00 – 0x00 0x00 – 53 ...
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... S1R72801F00A Address Register Name Bit Symbol 0x1E MaxRetry maxRty[3] 2: maxRty[2] 1: maxRty[1] 0: maxRty[0] Single Retry Limit Set Register This register sets the number of retries of the Single Phase Retry protocol. When its value is “0”, the Single Phase Retry is ignored. Bit7..4 Reserved Bit3 ...
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... Multiple Bus, Bus ID is uniquely specifying R Self Node's Physical ID Number R/W Description R/W 0: Normal 1: PHY Reg Rd Request R/W 0: Normal 1: PHY Reg Wr Request R/W PHY Register Read/Write Request Address EPSON S1R72801F00A H.Rst S.Rst B.Rst 0xFF – – – – 1 0xFF – H.Rst S.Rst B.Rst 0x00 0x00 – ...
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... S1R72801F00A Address Register Name Bit Symbol 0x25 PhyAccCtl_L 7: WrDat[7] 6: WrDAt[6] 5: WrDat[5] 4: WrDat[4] 3: WrDat[3] 2: WrDat[2] 1: WrDat[1] 0: WrDat[0] PHY Register Access Control Register (Lower Rank) Bit7..0 PHY Write Data Set data to write to the PHY Register. Address Register Name Bit Symbol 0x26 PhyRdstat_H 7: 6: ...
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... EPSON S1R72801F00A Description H.Rst S.Rst B.Rst 0x00 0x00 0x00 0x00 bit3 bit2 bit1 ch04 ch05 ch06 ch12 ch13 ch14 ch20 ch21 ...
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... S1R72801F00A Address Register Name 0x2A CmprIndex Compare Index[3] 2: Compare Index[2] 1: Compare Index[1] 0: Compare Index[0] 0x2B CmprWindow 7: Compare Window[7] 6: Compare Window[6] 5: Compare Window[5] 4: Compare Window[4] 3: Compare Window[3] 2: Compare Window[2] 1: Compare Window[1] 0: Compare Window[0] Compare Offset Address Index Window Register This register sets a compare offset address. ...
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... When the self node is a CYCLE TIMER and the DisCycTimer=“0” incremented in a cycle of 24.576MHz. When the Cycle Offset reaches 3072 restored to 0 and then the Cycle Count is incremented. Bit Symbol R/W R/W CYCLE_TIME.second_count R/W CYCLE_TIME.cycle_count R/W CYCLE_TIME.cycle_offset EPSON S1R72801F00A Description H.Rst S.Rst B.Rst 0x00 – 0x00 – 0x00 – 0x00 – ...
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... S1R72801F00A Address Register Name Bit Symbol 0x30 HwSBP2Ctl 7: PtNotPresent 6: HOSTtoDev 5: FromStream 4: 3: HwSBP2Rst 2: HwSBP2Rsum 1: HwSBP2Pause 0: HwSBP2Start Hardware SBP2 Control Register This register controls the SBP2 processing of this IC. Bit7 UltraDmaMode PtNotPresent:0 (Present) Set => PageTable exists. PtNotPresent:1 (Not Present) Set => PageTable does not exist. ...
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... It is cleared at the time of Reset. Writing to this bit is ignored.. R/W Description R 0: Not Firmware Pause 1: FirmWre Pause R 0: Not Error Pause 1: Error Pause Not Ready 1: Ready R 0: Stop 1: Execute R 0: Stop 1: Execute R 0: Stop 1: Execute R 0: Stop 1: Execute EPSON S1R72801F00A H.Rst S.Rst B.Rst 0x00 0x00 – 61 ...
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... S1R72801F00A Address Register Name Bit Symbol 0x32 HwSBP2IntStat 7: SplitTimeOut 6: TxAckedIllegal R(W) 0: None 5: TxAckMiss 4: BrAbort 3: 2: RxNotRespCmp R(W) 0: None 1: RxBroadCast R(W) 0: None 0: RxAckDataErr R(W) 0: None Hardware SBP2 Interrupt Status Register This register indicates error information when an error arises in execution of the hardware SBP2 processing. At the same time, it asserts the HwSBP2Err bit of the SubIntStat Register. When clearing it, write “1” bit to clear ...
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... HwSBP2 Window[10] 1: HwSBP2 Window[9] 0: HwSBP2 Window[8] R/W HwSBP2 Window 7: HwSBP2 Window[7] 6: HwSBP2 Window[6] 5: HwSBP2 Window[5] 4: HwSBP2 Window[4] 3: HwSBP2 Window[3] 2: HwSBP2 Window[2] 1: HwSBP2 Window[1] 0: HwSBP2 Window[0] EPSON S1R72801F00A Description H.Rst S.Rst B.Rst 0x00 0x00 0x00 0x00 0x00 0x00 – – – 63 ...
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... S1R72801F00A H/W SBP2 Index Chnnel/Window Register SBP2Index SBP2Window_H/L bit7 0x00 PageBoundary PageElementNunber 0x01 PgElmentRemain_H (MSB) PgElmentRemain_L 0x02 SpeedCode MaxPayload 0x03 DestinationID_H (MSB) DestinationID_L 0x04 SplitTime_H SplitTime_L 0x05 (Reserved) : (Reserved) 0x0F (Reserved) PageBoundary Set a value of page boundary to use for the HwSBP2. The actual page boundary is as follows. ...
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... Write is invalid. } R/W Description If (HwSBP2Ctl.PtNotPresent == 0) { Write:Set PageElement *8 (bytes) Read :Indicate Page Table Size } else { R/W Write:Set Data Length (bytes) Read :Indicate Create PageElement *8 (bytes) } EPSON S1R72801F00A H.Rst S.Rst B.Rst 0x00 0x00 – 0x00 0x00 – H.Rst S.Rst B.Rst 0x00 0x00 – 0x00 0x00 – ...
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... S1R72801F00A Address Register Name Bit Symbol 0x3A PageTableAdrs0 7: PtAdress[47] 6: PtAdress[46] 5: PtAdress[45] 4: PtAdress[44] 3: PtAdress[43] 2: PtAdress[42] 1: PtAdress[41] 0: PtAdress[40] 0x3B PageTableAdrs1 7: PtAdress[39] 6: PtAdress[38] 5: PtAdress[37] 4: PtAdress[36] 3: PtAdress[35] 2: PtAdress[34] 1: PtAdress[33] 0: PtAdress[32] 0x3C PageTableAdrs2 7: PtAdress[31] 6: PtAdress[30] 5: PtAdress[29] 4: PtAdress[28] 3: PtAdress[27] 2: PtAdress[26] 1: PtAdress[25] 0: PtAdress[24] 0x3D PaqeTableAdrs3 7: PtAdress[23] 6: PtAdress[22] 5: PtAdress[21] ...
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... Write is ignore Read is always zero Description Write is ignore Read is always zero R/W Current Received Packet ORB Data Area Pointer Write is ignore Read is always zero EPSON S1R72801F00A H.Rst S.Rst B.Rst 0x00 0x00 – 0x00 0x00 – H.Rst S.Rst B.Rst 0x00 0x00 – 0x00 0x00 – ...
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... S1R72801F00A Address Register Name Bit Symbol R/W 0x44 LinkRxStreamPtr_H PSP[12] 3: PSP[11] 2: PSP[10] 1: PSP[9] 0: PSP[8] 0x45 LinkRxStreamPtr_L 7: PSP[7] 6: PSP[6] 5: PSP[5] 4: PSP[4] 3: PSP[3] 2: PSP[ Receive Stream Data LINK Pointer Register This Receive Stream Data LINK Pointer Register indicates the starting address of the latest received stream data in the RxStreamdataArea. Since the buffer pointer is in Quadlet unit, the lower order 2 bits are always “ ...
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... Write is ignore Read is always zero Description Write is ignore Read is always zero R/W Received Packet ORB Data Area Used Pointer Write is ignore Read is always zero EPSON S1R72801F00A H.Rst S.Rst B.Rst 0x00 0x00 – 0x00 0x00 – H.Rst S.Rst B.Rst 0x00 0x00 – 0x00 0x00 – ...
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... S1R72801F00A Address Register Name Bit Symbol R/W 0x4C IDE_RxStreamPtr_H IRSP[12] 3: IRSP[11] 2: IRSP[10] 1: IRSP[9] 0: IRSP[8] 0x4D IDE_RxStreamPtr_L 7: IRSP[7] 6: IRSP[6] 5: IRSP[5] 4: IRSP[4] 3: IRSP[3] 2: IRSP[ Receive Stream Data IDE Pointer Register This Receive Stream Data IDE Pointer Register indicates the starting address of received stream data in the RxSTreamArea that transmitted to the IDE side but not yet transmitted. Since the buffer pointer is in Quadlet unit, the lower order 2 bits are always “ ...
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... None Affect 1: Tx Stream Data Clear W 0: None Affect 1: Rx Stream Data Clear W 0: None Affect 1: Rx ORB Dat Clear W 0: None Affect 1: Rx Header Clear None Affect 1: Update Link Tx Stream Ptr EPSON S1R72801F00A H.Rst S.Rst B.Rst 0x00 0x00 – 71 ...
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... S1R72801F00A Address Register Name Bit Symbol 0x51 BufMonitor 7: RxPayldRdy 6: TxPayldRdy RxHdrRemain 2: RxORBFull 1: RxStreamFull 0: RxHdrFull Buffer Monitor Register This Buffer Monitor Register indicates each buffer area status. This register is read-only. Writing to this register is ignored.. bit7 Rx Payload Ready When a free space the equivalent of the size set by the PyloadSize Register exists in the RxStreamArea, this bit becomes “ ...
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... If you read this bit, it always indicates “0” regardless of presence/absence of transmit. R/W Description R/W 0: AsyTxPktHdr0 1: AsyTxPktHdr1 Stream Area 0: AsyFIFO Empty 1: Non Empty W 0: Normal 1: AsyFIFO Clear R 0: Async Tx Stop 1: Async Tx Run W 0: normal 1: Async Start EPSON S1R72801F00A H.Rst S.Rst B.Rst 0x00 0x00 – 73 ...
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... S1R72801F00A Address Register Name Bit Symbol 0x53 IsoDmaCtl 7: IsoChnlSel SelTxPtr 3: IsoFIFOEpty 2: IsoFIFOClr 1: IsoTxMon 0: IsoStart ISO TxDMA Control Register Bit7 ISO Transmit Packet Header Channel Select Selects the header area of an ISO Transmit packet from DMA. You can transmit a transmit packet from the selected area. This bit selects “ ...
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... It means that a RxDmaCmp interrupt occurs if this packet has been correctly received. The Ack_busy is continuously returned to the subsequent receive packets. R/W Description FIFO Empty 1: Non Empty W 0: Normal 1: Rx FIFO Clear Stop 1: Rx Run R/W 0: Normal 1: Busy EPSON S1R72801F00A H.Rst S.Rst B.Rst 0x00 0x00 – 75 ...
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... S1R72801F00A Address Register Name Bit Symbol 0x55 AreaIndex MemMapIndex[3] 2: MemMapIndex[2] 1: MemMapIndex[1] 0: MemMapIndex[0] 0x56 AreaWindow_H 7: MemMapWindow[15] 6: MemMapWindow[14] 5: MemMapWindow[13] 4: MemMapWindow[12] 3: MemMapWindow[11] 2: MemMapWindow[10] 1: MemMapWindow[9] 0: MemMapWindow[8] 0x57 AreaWindow_L 7: MemMapWindow[7] 6: MemMapWindow[6] 5: MemMapWindow[5] 4: MemMapWindow[4] 3: MemMapWindow[3] 2: MemMapWindow[2] 1: MemMapWindow[1] 0: MemMapWindow[0] Memory Map Area Set Index Window Register This register is an Index Register and Window Register to set each area of a memory map ...
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... RxStreamAreaStart[7:2] R/W Description Write is ignore Read is always zero Bus Reset Header Area Pointer R This register indicates Address in Rx Header Area when BusRest detected. Write is ignore Read is always zero EPSON S1R72801F00A bit2 bit1 bit0 RxORBAreaStart[12:8] (LSB) TxHdrAreaStart[12:8] (LSB) TxStreamAreaStart[12:8] (LSB) TxStreamAreaEnd[12:8] (LSB) RxStreamAreaStart[12:8] (LSB) H ...
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... S1R72801F00A Address Register Name Bit Symbol 0x5A BRstORBPtr_H BusRstORBPtr[12] 3: BusRstORBPtr[11] 2: BusRstORBPtr[10] 1: BusRstORBPtr[9] 0: BusRstORBPtr[8] 0x5B BRstORBPtr_L 7: BusRstORBPtr[7] 6: BusRstORBPtr[6] 5: BusRstORBPtr[5] 4: BusRstORBPtr[4] 3: BusRstORBPtr[3] 2: BusRstORBPtr[ Bus Reset ORB Pointer Register This Bus Reset Header Pointer Register holds the value of a PostRxORBPtr when a bus reset occurs. When several bus resets occur updated to the latest PostRxORBPtr ...
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... Optional AckCode R/W Description 0: DMA Mode 1: Ultra DMA Mode 0: PIO Mode 1: DMA Mode 0: None 1: Active R/W 0: Master 1: Slave 0: Positive Logic 1: Negative Logic 0: Nomal 1: Swap IDE Port Hi & EPSON S1R72801F00A H.Rst S.Rst B.Rst 0x00 0x00 – H.Rst S.Rst B.Rst 0x00 0x00 – 79 ...
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... S1R72801F00A Address Register Name Bit Symbol 0x61 IDE_Config1 7: IDE_Reset IDE Configuration Register This register sets the mode of operation of the IDE interface of this IC. Bit7 IDE_Reset Writing “1” to this bit asserts the RESET signal to the IDE interface for 50 s. During asserting the XHRESET, this bit reads “ ...
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... IDE Transfer Mode Strobe Signal Assert Pulse Width Minimum Value IDE Transfer Mode Strobe Signal Negate Pulse Width Minimum Value R/W Description Minimum Cycle Time EPSON S1R72801F00A H.Rst S.Rst B.Rst 0x00 0x00 – H.Rst S.Rst B.Rst 0x00 0x00 – 81 ...
Page 86
... S1R72801F00A Address Register Name Bit Symbol 0x65 IDE_DmaCtl CRC_Clear 3: FIFO_Clear 2: IDE_Abort 1: IDE_Direction 0: DmaStart IDE DMA Control Register This register makes control when transferring data through the IDE interface. Bit7..5 Reserved Bit4 CRC_Clear Initializes the internal CRC calculation circuit. At start-up of the DMA, even the internal circuits are initialized . Writing “ ...
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... Indicates whether the DMA mode in execution is in execution or not enabled when the DmaRun bit is “1”. DmaPause:1 DMA is in execution. DmaPause:0 DMA is not in execution. R/W Description IDE DMA not Pause 1: IDE DMA Pause W 0: Not DMA 1: IDE DMA Running EPSON S1R72801F00A H.Rst S.Rst B.Rst 0x00 0x00 – 83 ...
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... S1R72801F00A Address Register Name Bit Symbol 0x68 IDE_ByteCount0 7: ByteCount[31] 6: ByteCount[30] 5: ByteCount[29] 4: ByteCount[28] 3: ByteCount[27] 2: ByteCount[26] 1: ByteCount[25] 0: ByteCount[24] 0x69 IDE_ByteCount1 7: ByteCount[23] 6: ByteCount[22] 5: ByteCount[21] 4: ByteCount[20] 3: ByteCount[19] 2: ByteCount[18] 1: ByteCount[17] 0: ByteCount[16] 0x6A IDE_ByteCount2 7: ByteCount[15] 6: ByteCount[14] 5: ByteCount[13] 4: ByteCount[12] 3: ByteCount[11] 2: ByteCount[10] 1: ByteCount[9] 0: ByteCount[8] 0x6B IDE_ByteCount3 7: ByteCount[7] 6: ByteCount[6] 5: ByteCount[5] ...
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... CRC[6] 5: CRC[5] 4: CRC[4] 3: CRC[3] 2: CRC[2] 1: CRC[1] 0: CRC[0] CRC Read Register This register indicates CRC calculation results when transferring data by the Ultra-DMA through the IDE interface. R/W Description R IDE CRC Data Register EPSON S1R72801F00A H.Rst S.Rst B.Rst 0x00 0x00 – 0x00 0x00 – 85 ...
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... S1R72801F00A Address Register Name Bit Symbol 0x70 IDE_CS00 0x71 IDE_CS01 UltraDmaMode 1: 0: 0x72 IDE_CS02 0x73 IDE_CS03 0x74 IDE_CS04 0x75 IDE_CS05 ...
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... R/W Read : Data Bus Hi – Impedance Write: Not Used Control Block Register R/W Read : Alternate Status Write: Device Control Control Block Register R/W Read : (obsolete) Write: Not Used EPSON S1R72801F00A Description H.Rst S.Rst B.Rst 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 ...
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... S1R72801F00A 8.2 FLASH ROM CONTROL REGISTER Address Register Name Bit Symbol 0x200000 FlashCtl 7: FlashCtlEnb Erase 3: FlashStat 2: FlashChipErs R/W 0: Chip All Erase Disable 1: FlashSctErs 0: FlashWrEnb Flash Control Register This register controls the erase and write of the built-in Flash. Bit7 FlashCtlEnb Enables Flash control. ...
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... FlashSctErs==1 && FlashWrEnb==0){ R/W Enable; Default Value = 0x0FFFFF; } erase if(FlashChipErs==0 && FlashSctErs==0 && FlashWrEnb==1){ R/W Enable; Default Value = 0x000190; } else { Read is alway Zero; Write is Ignore; } EPSON S1R72801F00A H.Rst S.Rst B.Rst 0x00 0x00 – 0x00 0x00 – 0x00 0x00 – 89 ...
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... S1R72801F00A Address Register Name Bit Symbol 0x200004 FlashAdrs_H 7: Flash Address[15] 6: Flash Address[14] 5: Flash Address[13] 4: Flash Address[12] 3: Flash Address[11] 2: Flash Address[10] 1: Flash Address[9] 0: Flash Address[8] R/W When Data register's Low Byte is accessed, 0x200005 FlashAdrs_M 7: Flash Address[7] 6: Flash Address[6] 5: Flash Address[5] 4: Flash Address[4] 3: Flash Address[3] ...
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... –0 OUT LV –0 OUT I –30 OUT T –65 to 150 STG Symbol Min. Typ TOPr1 0 TOPr2 0 EPSON S1R72801F00A Unit Max. Unit 5 5.5 V 3.3 3.6 V – – – – ...
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... S1R72801F00A 9.3 DC CHARACTERISTICS (ACCORDING TO RECOMMENDED OPERATING CONDITION) (1) Item Power supply current Power supply current Static current (Static current between HV Power supply current Static current (Static current between LV Power supply current Input leak Input leak current Input characteristics (CMOS) HIGH level input voltage V ...
Page 97
... BHL LV =3.0V BHH DD V =2.6V BHH Pin name: LINKON, SCLK, CTL0, CTL1, D0..D7, T18 LV =3.6V BHL DD I =0.9mA BHL LV =3.6V BHH DD I =–0.9mA BHH EPSON S1R72801F00A = 3.3V 0.3V Min. Typ. Max. –1 – 1 – – 0.3 –0.3 – – L –0.4 – – VDD – – ...
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... S1R72801F00A 9.4 AC CHARACTERISTICS 9.4.1 Clock Timing 9.4.1.1 SCLK Timing SCLK 9.4.1.2 HCLK Timing HCLK Symbol T SCLK frequency 201 T SCLK duty cycle 202 T SCLK start 203 T HCLK frequency 204 T HCLK duty cycle 205 94 T 201 T T 202 T 203 T 204 T 205 Description HCLK start delay time EPSON ...
Page 99
... SCLK rising edge 214 set-up time T SCLK rising edge 215 hold time T T 211 212 T T 214 212 Description C, Ctl, Output starts.) C, Ctl, C, Ctl, Description C, Ctl C, Ctl EPSON S1R72801F00A T 213 Unit Min. Max Unit Min. Max ...
Page 100
... Data hold time T HIORDY assert 329 XHDMACK set-up time 96 PORT T 321 323 324 325 T T 328 327 Specification HDA XHIOR EPSON S1R72801 HOST T 322 T 326 T 329 Min. Typ. Max. – 0 – – 0 – 60 – – – IDEPIO – (AP+2) 20 – ...
Page 101
... XHDMACK set-up time PORT T 331 333 334 335 T 337 T 338 Specification HDA XHIOW XHIOW XHIOW XHCS0 HDD HDD XHIOW EPSON S1R72801F00A S1R72801 HOST T 332 T 336 T 339 Min. Typ. Max. – 0 – – 0 – 60 – – IDEPIO – (AP+2) 20 – IDEPIO – ...
Page 102
... XHIOR HDD 34a Data bus hold time 98 Direction of DATA Transfer PORT T 341 T 343 345 346 T T 349 34a Specification XHDMACK XHDMACK XHIOR EPSON S1R72801 HOST T 342 T 344 T 347 348 Min. Typ. Max. 60 – – 25 – – 0 – – 0 – – 0 – ...
Page 103
... Direction of DATA Transfer PORT T 351 T 353 T T 355 356 T T 359 35a Specification XHDMACK XHCS0,1 XHDMACK HDMARQ negate XHIOW XHIOW XHIOW XHDMACK HDD EPSON S1R72801F00A S1R72801 HOST T 352 T 354 T T 357 358 Min. Typ. Max. 60 – – 20 – – 0 – – 0 – – 0 – ...
Page 104
... T 368 T 36f T 365 T 36a T 36b Specification XHDMACK XHCS0,1 XHDMACK XHIOR,XHIOW HIORDY HDMARQ XHIOR,XHIOWÅ™ XHIOR HDD HDD(CRC) HDMACK HDD(CRC) HIORDY EPSON S1R72801 HOST T 362 T 366 T 367 T 369 T 36c CRC T 36d Min. Typ. Max. 20 – – 40 – – 20 – – ...
Page 105
... T 374 T 375 T 379 T 376 T 37b Specification XHDMACK XHCS0,1 XHDMACK XHIOW HIORDY XHIOR XHIOR HDD HDD(CRC) HDMACK HDD(CRC) HIORDY EPSON S1R72801F00A PORT S1R72801 HOST T 372 T T 377 378 T 37a T 37e T 37c CRC T 37d Min. Typ. Max. 20 – – 40 – – 20 – ...
Page 106
... S1R72801F00A 9.4.4 CPU Interface Timing Regarding the built-in CPU, refer to the E0C33208/204/202 TECHNICAL MANUAL. In the built-in CPU core, however, a DMA controller and A/D converter are not integrated; this part is different from the description on the DMA controller and A/D converter given in TECHNICAL MANUAL. A low-speed oscillation circuit (OSC1) is not available ...
Page 107
... SE RESET AGND DD 50 AGND AGNG 49 0.01u C25 + C27 5.1K R37 220p EPSON S1R72801F00A C12 10P C11 10P 1000p C13 C29 C30 0.1u 0.01u C25 + C28 5.1K R38 8 1 C10 220p 103 ...
Page 108
... S1R72801F00A 1K 10K R63 10K R62 10K R61 10K R60 DD LV 139 N.C 140 TH3 TH P22 1 141 TH4 TH P23 1 142 K66 143 K67 144 XWAIT 145 CP2 CP P00 1 146 CP3 CP P01 1 147 V SS 148 CP4 CP P02 1 149 CP5 CP P03 1 150 CP6 CP P04 1 151 ...
Page 109
... D11 A14 20 A13 D12 A15 19 A14 D13 A16 18 A15 D14 D15 40 xUB 10K xLB xCS 17 xWE 41 xOE TC551664BFT EPSON S1R72801F00A D[0:15] (2H5 D10 36 D11 39 D12 41 D13 43 D14 45 D15 9 ...
Page 110
... S1R72801F00A 11. SHAPE OF PACKAGE Plastic QFP20-184 pin 139 184 106 22 0.4 20 0.1 138 INDEX 1 +0.05 0.4 0.16 –0.03 EPSON +0.05 0.125 –0.025 0 10 0.5 0.2 1 ...
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... International Sales Operations AMERICA EPSON ELECTRONICS AMERICA, INC. HEADQUARTERS 1960 E. Grand Avenue El Segundo, CA 90245, U.S.A. Phone : +1-310-955-5300 Fax : +1-310-955-5400 SALES OFFICES West 150 River Oaks Parkway San Jose, CA 95134, U.S.A. Phone : +1-408-922-0200 Fax : +1-408-922-0238 Central 101 Virginia Street, Suite 290 Crystal Lake, IL 60014, U.S.A. ...
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In pursuit of “Saving” Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers’ dreams. Epson IS energy savings. ...
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... S1R72801F00A Technical Manual This manual was made with recycle paper, and printed using soy-based inks. ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ First issue December,2000 Printed March,2001 in Japan A H ...