s1r72801 Epson Electronics America, Inc., s1r72801 Datasheet - Page 26

• Manufacturer Part Number: s1r72801
• Description: Ieee1394 Controller S1r72801f00a
• Manufacturer: Epson Electronics America, Inc.

S1R72801F00A
8.1.2 Register/Bit Table
The base address of this register is 0x100000.
22
Address Register Name
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
RetryLimit_L
MainIntStat
SubIntStat
(Reserved)
DmaIntStat
LinkIntStat1
LinkIntStat0
PhyIntStat
(Reserved)
MainIntEnb
SubIntEnb
(Reserved)
DmaIntEnb
LinkIntEnb1
UltraDmaMode
PhyIntEnb
(Reserved)
ChipCtl
HW_Revision
ApetusTestOutPut_H
ApetusTestOutPut_L
LCTestIndex
LCTestWindow
SBP2TestIndex
SBP2TestWindow
LinkCtl_H
LinkCtl_L
LinkStat
PriReqCnt
RetryLimit_H
MaxRetry
IRM_Stat
NODE_IDS_H
NODE_IDS_L
(Reserved)
(Reserved)
PhyAccCtl_H
PhyAccCtl_L
PhyRdstat_H
PhyRdstat_L
ChnlIndex
ChnlWindow
CmprIndex
CmprWindow
CYCLE_TIME_H
CYCLE_TIME_MH
CYCLE_TIME_ML
CYCLE_TIME_L
EnSelfIDdone EnSelfIDerr EnHwSBP2Err EnHwSBP2BRst EnLinkIntStat1 EnLinkIntStat0 EnPhyIntStat EnDmaIntStat
EnSubIntStat EnTxIsoCmp EnRxDmaCmp EnTxAsyCmp EnHwSBP2Cm EnIDE_DmaC EnIDE_INTRQ EnBusReset
EnUnExpCh
SelfIDdone
PassSelfID
EnSubGap
SubIntStat
UnExpCh
Suspend
SubGap
RdReq
EnLink
NoIRM
bit7
BusID[1:0]
EnTxAsyRtyGo EnTxAsyBCSe EnRxDmaFaild EnTxAsyFaild EnTxIsoFaild EnTxAsyBRAb EnTxAsyMiss
SecLimit[2:0]
TxAsyRtyGo TxAsyBCSent RxDmaFaild
PassPhyPkt
EnDupliCh
EnArbGap
TxIsoCmp
SelfIDerr
WonIRM
DupliCh
ArbGap
WrReq
bit6
Cycle Count[3:0]
EnIsoArbFaild EnCycTooLon EnCycOverFlw EnCycEvent
HwSBP2Err HwSBP2BRs LinkIntStat1
RxDmaCmp
IsoArbFaild
PassBrPkt
PLIFrst
bit5
EPSON
Cycle Second[6:0]
CycTooLong CycOverFlw
Compare Address Window
TxAsyCmp
Chip Test Register
EnPosWB
IgnrBChdr
bit4
HW_Revision[7:0]
Cycle Count[11:4]
Channel Window
Cycle Offset[7:0]
CycLimit[7:0]
Write Data[7:0]
Read Data[7:0]
BusID[9:2]
Priority Budget Request Count [5:0]
EnRxOnTardy EnRxHcrcErr EnRxUnkTcod EnTxRtyExced
HwSBP2Cmp IDE_DmaCm IDE_INTRQ
RxOnTardy
TxAsyFaild
IgnrBCdata
EnPosWQ
bit3
Physical ID[5:0]
IRM_ID[5:0]
CycLimit[12:8]
RxBusyMode
LinkIntStat0
IDE_MdlRst
TxIsoFaild
RxHcrcErr
EnPhy_int EnPhyWrDone EnPhyRdDone
CycEvent
ID_Valid
Compare Address Index
Phy_int
APHY
Request Address[3:0]
bit2
Read Address[3:0]
Channel Index
MaxRetry[3:0]
Cycle Offset[11:8]
TxAsyBRAbort TxAsyMiss
RxUnkTcode
PhyWrDone
DualRtyEnb
SendTardy
EnCycLost
PhyIntStat
CycLost
EnAcc
bit1
Root
EnCycArbFail
SinglRtyEnb
TxRtyExced
PhyRdDone
DmaIntStat
CycCnt[12]
CycArbFail
CablPwSts
BusReset
SoftReset
Cmstr
bit0