s1r72801 Epson Electronics America, Inc., s1r72801 Datasheet - Page 55

• Manufacturer Part Number: s1r72801
• Description: Ieee1394 Controller S1r72801f00a
• Manufacturer: Epson Electronics America, Inc.

Hardware Revision Register
LINK Core Control Register Higher Rank
Bit7 Pass Self-ID Packet
Bit6 Pass PHY Packet
Bit5 Pass BusReset Packet
Bit4 Enable Posted Block Write
Bit3 Enable Posted Quadlet Write
Bit2 APHY
Bit1 Enable Ack Acceleration
Bit0 cmstr
Address Register Name
Address Register Name
0x11
0x18
The HW_Revision Register indicates the revision number of a chip.
This register controls the functions of the LINK core.
Setting this bit to “1” captures a Self-ID packet received by the LINK core into the buffer.
When requesting the PHY Register for a register write, this bit is set to “1”. After the execution, this bit is
cleared.
Setting this bit to “1” captures a BusReset packet received by the LINK core into the buffer.
Setting this bit to “1” enables the Posted Write function for a Block Write Request.
Setting this bit to “1” enables the Posted Write function for a Quadlet Write Request.
Indicates whether the PHY conforms to 1394.a or not.
1: Conforms to PHY 1394.a
0: Does not conform to PHY 1394.a
Indicates the setting of Ack Acceleration.
1: Ack Acceleration enable
0: Ack Acceleration disable
When the self node is Cycle Master capable and a root, this bit becomes “1”.
If the self node does not become a root in the Self-ID processing when this bit is set after the Bus Reset, this
bit is cleared.
HW_Revision
LinkCtl_H
7: HW_Revision[7]
6: HW_Revision[6]
5: HW_Revision[5]
4: HW_Revision[4]
3: HW_Revision[3]
2: HW_Revision[2]
1: HW_Revision[1]
0: HW_Revision[0]
7: PassSelfID
6: PassPhyPkt
5: PassBrPkt
4: EnPosWB
3: EnPosWQ
2: APHY
1: EnAcc
0: Cmstr
Bit Symbol R/W
Bit Symbol
R/W 0: Disable Posted WB
0: Non PassSelfID
0: Non Pass PHY Packet 1: PHY Pkt to DMA FIFO
0: Non Pass BusRst Packet
0: Disable Poosted WQ
0: PHY 1394.a uncorrespond 1: PHY 1394.a correspond
0: Ack Acceleration Disable 1: Ack Acceleration Enable
0: Cycle Master Not Capabl 1: Cycle Master Capable
R/W
R
EPSON
Indicate Hard Ware Revison Number
Description
Description
1: Self–ID to DMA FIFO
1: BusRst Pkt to DMA FIFO
1: Enable Posted WB
1: Enable Posted WQ
H.Rst S.Rst B.Rst
S1R72801F00A
0x03 0x03 0x03
H.Rst S.Rst B.Rst
0x00
0x00
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