s1r72801 Epson Electronics America, Inc., s1r72801 Datasheet - Page 66

• Manufacturer Part Number: s1r72801
• Description: Ieee1394 Controller S1r72801f00a
• Manufacturer: Epson Electronics America, Inc.

S1R72801F00A
Hardware SBP2 Interrupt Status Register
Bit7 Split Timeout
Bit6 Tx Acked Illegal
Bit5 Tx Ack Miss
Bit4 BRAbort
Bit3 Reserved
Bit2 RxNotRespCmp
Bit1 RxBroadcast
Bit0 RxAckDataError
62
Address Register Name
0x32
This register indicates error information when an error arises in execution of the hardware SBP2 processing.
At the same time, it asserts the HwSBP2Err bit of the SubIntStat Register. When clearing it, write “1” to a bit
to clear.
This register is automatically cleared when setting HwSBP2Ctl.HwSBP2Start or the HWSBP2Ctl. HwSBP2Rst.
• SplitTimeOut:1 => During the HwSBP2 processing, an SPLIT TIMEOUT error arose.
TxAckedIllegal:1 => Though a transmission was completed, a response other than ack_pending was given to
a BlkRdReq and a response other than ack_completed was given to a BlkWrReq.
• TxAsyMiss:1 => Though a transmission was completed, no Ack was returned.
• When the HwSBP2Ctl.HwSBP2Start bit is set to “1” or HWSBP2Ctl.Resume bit is set to “1” during the
• RxNotRespCmp:1 => Though a response packet receive was completed, its code was other than resp_complete.
• RxBroadCast:1 => Though a response packet receive was completed, it was a broadcast packet.
• RxAckDataErr:1 => Though a response packet was received, it was a DataCRCError. It does not assert the
BusReset period, this bit becomes “1”,
interrupt signal SBP2Err. It is automatically cleared on completion of the Transaction.
HwSBP2IntStat 7: SplitTimeOut
6: TxAckedIllegal R(W) 0: None
5: TxAckMiss
4: BrAbort
3:
2: RxNotRespCmp R(W) 0: None
1: RxBroadCast R(W) 0: None
0: RxAckDataErr R(W) 0: None
Bit Symbol
R(W) 0: None
R(W) 0: None
R(W) 0: None
R/W
EPSON
0:
Description
1: SplitTimeOut
1: TxAckedIllegal
1: TxAsyMiss
1: BrAbort
1:
1: RxNotRespCmp
1: RxBroadCast
1: RxAckDataErr
H.Rst S.Rst B.Rst
0x00 0x00
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