peb20542 Infineon Technologies Corporation, peb20542 Datasheet - Page 212

• Manufacturer Part Number: peb20542
• Description: 2 Channel Serial Optimized Communication Controller With Dma
• Manufacturer: Infineon Technologies Corporation

Data Sheet
AMRAH2
AMRAL2
AMRAH1
AMRAL1
Receive Mask Address 2 Byte High
Receive Mask Address 2 Byte Low
Receive Mask Address 1 Byte High
Receive Mask Address 1 Byte Low
Setting a bit in this registers to ’1’ masks the corresponding bit in
registers RAH2/RAL2/RAH1/RAL1. A masked bit position always
matches when comparing the received frame address with registers
RAH2/RAL2/RAH1/RAL1, allowing extended broadcast mechanism.
bit = ’0’
bit = ’1’
The dedicated bit position is NOT masked. This bit
position in the received address must match with the
corresponding bit position in registers RAH2/RAL2/RAH1/
RAL1
The dedicated bit position is masked. This bit position in
the received address NEED NOT match with the
corresponding bit position in registers RAH2/RAL2/RAH1/
RAL1
to accept the frame.
to accept the frame.
5-212
Register Description (AMRAH2)
(hdlc modes)
(hdlc modes)
(hdlc modes)
(hdlc modes)
PEB 20542
PEF 20542
2000-09-14