peb20542 Infineon Technologies Corporation, peb20542 Datasheet - Page 287

• Manufacturer Part Number: peb20542
• Description: 2 Channel Serial Optimized Communication Controller With Dma
• Manufacturer: Infineon Technologies Corporation

7.7.2.2
Figure 80
Table 27
No. Parameter
90
91
92
Data Sheet
Receive
data rates
(1) Whichever supplies the receive clock depending on the selected clock mode:
(2) NRZ, NRZI and Manchester data encoding
(3) FM0 and FM1 data encoding
(4) If Carrier Detect auto start feature enabled (not for clock modes 1, 4 and 5)
Receive Clock
externally clocked via RxCLK or XTAL1 or
internally clocked via DPLL, BCR or BRG.
(No edge relation can be measured if the internal receive clock is derived from the external clock
source by division stages (BRG, BCR) or DPLL)
Clock
period
RxD to RxCLK setup time
RxD to RxCLK hold time
(Note 1)
(Note 2)
(Note 3)
(Note 4)
Receive Cycle Timing
RxD
RxD
Receive Cycle Timing
Receive Cycle Timing
CD
externally clocked
(HDLC)
internally clocked
(DPLL modes)
internally clocked
(non DPLL modes)
externally clocked
internally clocked
(DPLL modes)
internally clocked
(non DPLL modes)
91
93
92
287
91
91
90
94
92
92
min.
0
0
0
62
480
62
5
5
Electrical Characteristics
Limit Values
max.
16
2
16
¥
¥
¥
PEB 20542
PEF 20542
2000-09-14
Unit
Mbit/s
Mbit/s
Mbit/s
ns
ns
ns
ns
ns