74vcx16835 Fairchild Semiconductor, 74vcx16835 Datasheet
74vcx16835
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74vcx16835 Summary of contents
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... Ouputs (O n Positive Edge Transition of the Clock. When OE is LOW, the output data is enabled. When OE is HIGH the output port high impedance state. The 74VCX16835 is designed for low voltage (1.65V to 3.6V) V applications with I/O capability up to 3.6V. CC The 74VCX16835 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain- ing low CMOS power dissipation ...
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Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA (Top Thru View) www.fairchildsemi.com Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW) LE Latch Enable Input CLK Clock Input Data Inputs ...
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Logic Diagram 3 www.fairchildsemi.com ...
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Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATE Outputs Active (Note 7) 0 Input Diode Current ( Output ...
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DC Electrical Characteristics (2.3V Symbol Parameter V HIGH Level Input Voltage IH V LOW Level Input Voltage IL V HIGH Level Output Voltage OH V LOW Level Output Voltage OL I Input Leakage Current I I 3-STATE Output Leakage OZ ...
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AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX t , Propagation Delay PHL t Bus to Bus PLH t , Propagation Delay PHL t Clock to Bus PLH t , Propagation Delay PHL Bus PLH ...
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Capacitance Symbol Parameter C Input Capacitance IN C Input/Output Capacitance I/O C Power Dissipation Capacitance Characteristics OUT OUT FIGURE 1. Characteristics for Output - Pull Up Driver FIGURE 2. Characteristics for Output - Pull Down Driver ...
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AC Loading and Waveforms TEST PLH PHL PZL PLZ PZH PHZ FIGURE 4. Waveform for Inverting and Non-inverting Functions t t 2.0ns, 10 FIGURE 6. 3-STATE Output ...
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Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A Preliminary 9 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...