74vcx16821 Fairchild Semiconductor, 74vcx16821 Datasheet
74vcx16821
Related parts for 74vcx16821
74vcx16821 Summary of contents
Page 1
... Tolerant Inputs and Outputs General Description The VCX16821 contains twenty non-inverting D-type flip- flops with 3-STATE outputs and is intended for bus oriented applications. The 74VCX16821 is designed for low voltage (1.4V to 3.6V) V applications with I/O compatibility up to 3.6V. CC The 74VCX16821 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain- ing low CMOS power dissipation ...
Page 2
Connection Diagram Logic Diagrams Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com Truth Tables Inputs CLK OE D – ...
Page 3
Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATE Outputs Active (Note 3) 0. Input Diode Current ( Output ...
Page 4
DC Electrical Characteristics Symbol Parameter V LOW Level Output Voltage OL I Input Leakage Current I I 3-STATE Output Leakage OZ I Power-OFF Leakage Current OFF I Quiescent Supply Current CC I Increase in I per Input CC CC Note ...
Page 5
AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency C MAX Propagation Delay C PHL L t PLH Output Enable Time C PZL L t PZH Output Disable Time C ...
Page 6
Dynamic Switching Characteristics Symbol Parameter V Quiet Output Dynamic Peak V OLP OL V Quiet Output Dynamic Valley V OLV OL V Quiet Output Dynamic Valley V OHV OH Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance OUT ...
Page 7
AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low ...
Page 8
AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 8. Waveform for Inverting and FIGURE 9. 3-STATE Output High Enable and Disable Times for Low Voltage Logic ...
Page 9
Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...