74vcx16500 Fairchild Semiconductor, 74vcx16500 Datasheet
74vcx16500
Related parts for 74vcx16500
74vcx16500 Summary of contents
Page 1
... HIGH and OEBA is active LOW). The VCX16500 is designed for low voltage (1.4V to 3.6V) V applications with I/O capability up to 3.6V. CC The 74VCX16500 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain- ing low CMOS power dissipation. Ordering Code: Order Number Package Number ...
Page 2
Connection Diagram www.fairchildsemi.com Pin Descriptions Pin Names Description OEAB Output Enable Input for Direction (Active HIGH) OEBA Output Enable Input for Direction (Active LOW) LEAB, LEBA Latch Enable Inputs CLKAB, Clock Inputs CLKBA A ...
Page 3
Logic Diagram 3 www.fairchildsemi.com ...
Page 4
Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATED Outputs Active (Note 6) 0 Input Diode Current ( Output ...
Page 5
DC Electrical Characteristics Symbol Parameter V LOW Level Output Voltage OL I Input Leakage Current I I 3-STATE Output Leakage OZ I Power Off Leakage Current OFF I Quiescent Supply Current CC I Increase in I per Input CC CC ...
Page 6
AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency C MAX C t Propagation Delay C PHL t Bus-to-Bus PLH C t Propagation Delay C PHL t Clock-to-Bus PLH C t Propagation Delay C PHL t LE-to-Bus PLH C t ...
Page 7
Dynamic Switching Characteristics Symbol Parameter V Quiet Output Dynamic OLP Peak Quiet Output Dynamic OLV Valley Quiet Output Dynamic OHV Valley V OH Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance I/O ...
Page 8
AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 2. Waveform for Inverting and Non-inverting Functions FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low ...
Page 9
AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 8. Waveform for Inverting and Non-inverting Functions FIGURE 9. 3-STATE Output High Enable and Disable Times for Low ...
Page 10
Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...