74vcx16601 Fairchild Semiconductor, 74vcx16601 Datasheet

74vcx16601

Manufacturer Part Number

74vcx16601

Description

74vcx16601 Low Voltage 18-bit Universal Bus Transceivers With 3.6v Tolerant Inputs And Outputs

Manufacturer

Fairchild Semiconductor

Datasheet

1.74VCX16601.pdf (11 pages)

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Company:

Meier Automation Equipment Co., Limited

Part Number:

74VCX16601

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FAIRCHILD/仙童

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20 000

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74VCX16601GX

(Note 2)

74VCX16601MTD

(Note 3)

74VCX16601

Low Voltage 18-Bit Universal Bus Transceivers

with 3.6V Tolerant Inputs and Outputs

General Description

The VCX16601 is an 18-bit universal bus transceiver which

combines D-type latches and D-type flip-flops to allow data

flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable

(OEAB and OEBA), latch-enable (LEAB and LEBA), and

clock (CLKAB and CLKBA) inputs. The clock can be con-

trolled by the clock-enable (CLKENAB and CLKENBA)

inputs. For A-to-B data flow, the device operates in the

transparent mode when LEAB is HIGH. When LEAB is

LOW, the A data is latched if CLKAB is held at a HIGH-to-

LOW logic level. If LEAB is LOW, the A bus data is stored

in the latch/flip-flop on the LOW-to-HIGH transition of

CLKAB. When OEAB is LOW, the outputs are active. When

OEAB is HIGH, the outputs are in the high-impedance

state.

Data flow for B to A is similar to that of A to B but uses

OEBA, LEBA, CLKBA and CLKENBA.

The VCX16601 is designed for low voltage (1.4V to 3.6V)

The VCX16601 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Ordering Code:

Note 2: BGA package available in Tape and Reel only.

Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Order Number

applications with I/O capability up to 3.6V.

Package Number

(Preliminary)

BGA54A

MTD56

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

DS500126

Features

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to V

value of the resistor is determined by the current-sourcing capability of the

driver.

1.4V to 3.6V V

3.6V tolerant inputs and outputs

Power-down high impedance inputs and outputs

Supports live insertion/withdrawal (Note 1)

Static Drive (I

Uses patented noise/EMI reduction circuitry

Latchup performance exceeds 300 mA

ESD performance:

Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA) (Preliminary)

2.9 ns max for 3.0V to 3.6V V

Human body model

Machine model 200V

24 mA @ 3.0V V

(A to B, B to A)

Package Description

supply operation

)

2000V

through a pull-up resistor; the minimum

March 1998

Revised October 2004

www.fairchildsemi.com

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74vcx16601 Summary of contents

Page 1

... BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide (Note 2) (Preliminary) [TAPE and REEL] 74VCX16601MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide (Note 3) Note 2: BGA package available in Tape and Reel only. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

Page 2

Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA (Top Thru View) www.fairchildsemi.com Pin Descriptions Pin Names Description OEAB, OEBA Output Enable Inputs (Active LOW) LEAB, LEBA Latch Enable Inputs CLKAB, CLKBA Clock Inputs CLKENAB, CLKENBA Clock Enable Inputs ...

Page 3

Logic Diagram 3 www.fairchildsemi.com ...

Page 4

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-Stated Outputs Active (Note 8) 0 Input Diode Current ( Output ...

Page 5

DC Electrical Characteristics Symbol Parameter V LOW Level Output Voltage OL I Input Leakage Current I I 3-STATE Output Leakage OZ I Power Off Leakage Current OFF I Quiescent Supply Current CC I Increase in I per Input CC CC ...

Page 6

AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency C MAX C t Propagation Delay C PHL t Bus-to-Bus PLH C t Propagation Delay C PHL t Clock-to-Bus PLH C t Propagation Delay C PHL t LE-to-Bus PLH C t ...

Page 7

Dynamic Switching Characteristics Symbol Parameter V Quiet Output Dynamic Peak V OLP OL V Quiet Output Dynamic Valley V OLV OL V Quiet Output Dynamic Valley V OHV OH Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance I/O ...

Page 8

AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 2. Waveform for Inverting and Non-inverting Functions FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low ...

Page 9

AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 8. Waveform for Inverting and Non-inverting Functions FIGURE 9. 3-STATE Output High Enable and Disable Times for Low ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide www.fairchildsemi.com Package Number BGA54A (Preliminary) 10 ...

Page 11

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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