74vcx32500 Fairchild Semiconductor, 74vcx32500 Datasheet

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74vcx32500

Manufacturer Part Number
74vcx32500
Description
74vcx32500 Low Voltage 36-bit Universal Bus Transceivers With 3.6v Tolerant Inputs And Outputs
Manufacturer
Fairchild Semiconductor
Datasheet

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© 2003 Fairchild Semiconductor Corporation
74VCX32500G
(Note 2)(Note 3)
74VCX32500
Low Voltage 36-Bit Universal Bus Transceivers
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX32500 is an 36-bit universal bus transceiver which
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is
HIGH. When LEAB is LOW, the A data is latched if CLKAB
is held at a HIGH or LOW logic level. If LEAB is LOW, the A
bus data is stored in the latch/flip-flop on the HIGH-to-LOW
transition of CLKAB. When OEAB is HIGH, the outputs are
active. When OEAB is LOW, the outputs are in a high-
impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active HIGH and OEBA is active
LOW).
The VCX32500 is designed for low voltage (1.4V to 3.6V)
V
The 74VCX32500 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Ordering Code:
Note 2: Ordering Code “G” indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number
CC
applications with I/O capability up to 3.6V.
Package Number
BGA114A
114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
DS500403
Features
Note 1: To ensure the high-impedance state during power up or power
down, OEBA should be tied to V
should be tied to GND through a pull-down resistors; the minimum value of
the resistor is determined by the current-sourcing capability of the driver.
1.4V to 3.6V V
3.6V tolerant inputs and outputs
t
Power-down high impedance inputs and outputs
Supports live insertion/withdrawal (Note 1)
Static Drive (I
Uses patented noise/EMI reduction circuitry
Latchup performance exceeds 300 mA
ESD performance:
Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
PD
2.9 ns max for 3.0V to 3.6V V
Human body model
Machine model 200V
24 mA @ 3.0V V
(A to B, B to A)
Package Description
OH
CC
/I
OL
supply operation
)
CC
CC
2000V
through a pull-up resistor and OEAB
March 2001
Revised August 2003
CC
www.fairchildsemi.com

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74vcx32500 Summary of contents

Page 1

... HIGH and OEBA is active LOW). The VCX32500 is designed for low voltage (1.4V to 3.6V) V applications with I/O capability up to 3.6V. CC The 74VCX32500 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain- ing low CMOS power dissipation. Ordering Code: Order Number Package Number ...

Page 2

Connection Diagram (Top Thru View) Pin Descriptions Pin Names Description OEAB Output Enable Input for Direction n (Active HIGH) OEBA Output Enable Input for Direction n (Active LOW) LEAB , LEBA Latch Enable Inputs ...

Page 3

Logic Diagrams 3 www.fairchildsemi.com ...

Page 4

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATE Outputs Active (Note 8) 0 Input Diode Current ( Output ...

Page 5

DC Electrical Characteristics Symbol Parameter V LOW Level Output Voltage OL I Input Leakage Current I I 3-STATE Output Leakage OZ I Power Off Leakage Current OFF I Quiescent Supply Current CC I Increase in I per Input CC CC ...

Page 6

AC Electrical Characteristics Symbol Parameter t Setup Time Hold Time Pulse Width Note 11: For C 50pF, add approximately 300ps to the AC ...

Page 7

AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 2. Waveform for Inverting and Non-inverting Functions FIGURE 3. 3-STATE Output High Enable and Disable Times for Low ...

Page 8

AC Loading and Waveforms (V t PLH t PZL t PZH FIGURE 8. Waveform for Inverting and Non-Inverting Functions FIGURE 9. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 10. 3-STATE Output Low Enable and Disable ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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