sta339bw STMicroelectronics, sta339bw Datasheet - Page 31

• Manufacturer Part Number: sta339bw
• Description: 2.1-channel High-efficiency Digital Audio System
• Manufacturer: STMicroelectronics

STA339BW
Table 20.
To make the STA339BW work properly, the serial audio interface LRCKI clock must be
synchronous to the PLL output clock. It means that:
!
!
If these two conditions are not met, and bit IDE of register address 0x05 is set to 1, the
STA339BW immediately mutes the I
it freezes any active processing task.
To avoid any audio side effects (like pop noise), it is strongly recommended to soft mute any
audio streams flowing into STA339BW data path before the desynchronization event
32 * fs
48 * fs
64 * fs
the frequency of PLL clock / frequency of LRCKI = N ±4 cycles,
where N depends on the settings in
the PLL must be locked.
BICKI
Supported serial audio input formats for LSB-first (SAIFB = 1)
1100
1110
0100
0100
1000
1100
0001
0101
1001
1101
0010
0110
1010
1110
0000
0100
1000
1100
0001
0101
1001
1101
0010
0110
1010
1110
SAI [3:0]
Doc ID 15251 Rev 4
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
S PCM data out (provided to the processing block) and
SAIFB
Table 13 on page 28
I
Left/right-justified 16-bit data
I
I
I
LSB first I
Left-justified 24-bit data
Left-justified 20-bit data
Left-justified 18-bit data
Left-justified 16-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
I
I
I
LSB first I
Left-justified 24-bit data
Left-justified 20-bit data
Left-justified 18-bit data
Left-justified 16-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
2
2
2
2
2
2
2
S 15-bit data
S 23-bit data
S 20-bit data
S 18-bit data
S 24-bit data
S 20-bit data
S 18-bit data
2
2
S 16-bit data
S 16-bit data
Interface format
Register description
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