sta339bw STMicroelectronics, sta339bw Datasheet - Page 65

• Manufacturer Part Number: sta339bw
• Description: 2.1-channel High-efficiency Digital Audio System
• Manufacturer: STMicroelectronics

STA339BW
6.17
6.18
EQ coefficients and DRC configuration register (addr 0x31)
Table 74.
Bits AMGC[3:2] change the behavior of the bits AMGC[1:0] as given in
Table 75.
When AMGC[3:2] = 01 then the bits 1:0 are defined as given here in
Table 76.
AC0, AC1, AC2 settings are designed for the loudspeaker protection function, limiting at the
minimum any audio artefacts introduced by typical anti-clipping/DRC algorithms. More
detailed information is available in the applications notes “Configurable output power rate
using STA335BW” and “STA335BWS vs STA335BW”.
Bit XOB can be used to bypass the crossover filters. Logic 1 means that the function is not
active. In this case, high pass crossover filter works as a passtrough on the data path
(b0 = 1, all the other coefficients at logic 0) while the low pass filter is configured to have
zero signal on channel-3 data processing (all the coefficients are at logic 0).
Extended configuration register (addr 0x36)
Extended configuration register provides access to B
00/11
01
10
00
01
10/11
00
01
10
11
Mdrc[1]
XOB
D7
D7
0
0
AMGC[3:2]
AMGC[1:0]
SEL[1:0]
EQ RAM select
Anti-clipping and DRC preset
Anti-clipping selection for AMGC[3:2] = 01
Mdrc[0]
D6
D6
0
0
Reserved
PS48DB
Bank 0 activated
Bank 1 activated
Bank 2 activated
DRC/Anti-clipping behavior described in
DRC/Anti-clipping behavior is described in
Reserved, do not use
AC0, stereo anticlipping 0 dB limiter
AC1, stereo anticlipping +1.25 dB limiter
AC2, stereo anticlipping +2 dB limiter
Reserved do not use
D5
D5
0
0
Doc ID 15251 Rev 4
AMGC[3]
XAR1
D4
D4
0
0
Anti-clipping and DRC preset selected
EQ RAM bank selected
AMGC[2]
XAR2
D3
D3
0
0
2
DRC and biquads 5, 6 and 7.
Mode
Reserved
BQ5
D2
D2
Table 55 on page 47
0
0
Table 76
Table
Register description
Table 75
SEL[1]
below
BQ6
D1
D1
0
0
76.
below.
(default).
SEL[0]
BQ7
D0
D0
0
0
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