74lcx162374 Fairchild Semiconductor, 74lcx162374 Datasheet

74lcx162374

Manufacturer Part Number

74lcx162374

Description

Low Voltage 16-bit D-type Flip-flop With 5v Tolerant Inputs And Outputs And 26 ?series Resistors

Manufacturer

Fairchild Semiconductor

Datasheet

1.74LCX162374.pdf (10 pages)

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74LCX162374GX

(Note 2)

74LCX162374MEA

(Note 3)

74LCX162374MTD

(Note 3)

74LCX162374

Low Voltage 16-Bit D-Type Flip-Flop

with 5V Tolerant Inputs and Outputs

and 26 Ω Series Resistors

General Description

The LCX162374 contains sixteen non-inverting D-type

flip-flops with 3-STATE outputs and is intended for bus ori-

ented applications. The device is byte controlled. A buff-

ered clock (CP) and Output Enable (OE) are common to

each byte and can be shorted together for full 16-bit opera-

tion.

The LCX162374 is designed for low voltage (2.5V or 3.3V)

environment. The 26 Ω series resistor in the output helps

reduce output overshoot and undershoot.

The LCX162374 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing CMOS low power dissipation.

Ordering Code:

Note 2: BGA package available in Tape and Reel only.

Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

Order Number

applications with capability of interfacing to a 5V signal

Package Number

(Preliminary)

BGA54A

MS48A

MTD48

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

DS500442

Features

I 5V tolerant inputs and outputs

I 2.3V–3.6V V

I Equivalent 26 Ω series resistor on outputs

I 7.0 ns t

I Power down high impedance inputs and outputs

I Supports live insertion/withdrawal (Note 1)

I ± 12 mA output drive (V

I Implements patented noise/EMI reduction circuitry

I Latch-up performance exceeds 500 mA

I ESD performance:

I Also packaged in plastic Fine-Pitch Ball Grid Array

Note 1: To ensure the high-impedance state during power up or down, OE

should be tied to V

resistor is determined by the current-sourcing capability of the driver.

(FBGA) (Preliminary)

Human body model > 2000V

Machine model > 200V

Package Description

max (V

through a pull-up resistor: the minimum value or the

specifications provided

= 3.3V), 20 µ A I

= 3.0V)

February 2001

Revised August 2001

www.fairchildsemi.com

max

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74lcx162374 Summary of contents

Page 1

... REEL] 74LCX162374MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide (Note 3) 74LCX162374MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide (Note 3) Note 2: BGA package available in Tape and Reel only. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

Page 2

Connection Diagrams Pin Assignment for SSOP and TSSOP Pin Assignment for FBGA (Top Thru View) www.fairchildsemi.com Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW Clock Pulse Input n I –I Inputs –O ...

Page 3

Functional Description The LCX162374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte func- tioning identically, but independent of the other. The control pins can be shorted together ...

Page 4

Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Source/Sink Current Supply ...

Page 5

DC Electrical Characteristics Symbol Parameter I Power-Off Leakage Current OFF I Quiescent Supply Current CC ∆I Increase in I per Input CC CC Note 7: Outputs disabled or 3-STATE only. AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX ...

Page 6

AC LOADING and WAVEFORMS FIGURE 1. AC Test Circuit (C Test PLH PZL PZH Waveform for Inverting and Non-Inverting Functions Propagation Delay. Pulse Width and t rec 3-STATE Output Low Enable ...

Page 7

Schematic Diagram Generic for LCX Family 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide www.fairchildsemi.com Package Number BGA54A Preliminary 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 9 www.fairchildsemi.com ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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