74lcx162373 Fairchild Semiconductor, 74lcx162373 Datasheet

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74lcx162373

Manufacturer Part Number
74lcx162373
Description
74lcx162373 Low Voltage 16-bit Transparent Latch With 5v Tolerant Inputs And Outputs And 26w Series Resistor
Manufacturer
Fairchild Semiconductor
Datasheet

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© 2005 Fairchild Semiconductor Corporation
74LCX162373GX
(Note 2)
74LCX162373MEA
(Note 3)
74LCX162373MTD
(Note 3)
74LCX162373
Low Voltage 16-Bit Transparent Latch
with 5V Tolerant Inputs and Outputs
and 26: Series Resistor
General Description
The LCX162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear transparent to the data when the Latch Enable (LE)
is HIGH. When LE is LOW, the data that meets the setup
time is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
The LCX162373 is designed for low voltage (2.5V or 3.3V)
V
environment. The 26
reduce output overshoot and undershoot.
The LCX162373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Ordering Code:
Note 2: BGA package available in Tape and Reel only.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Order Number
CC
applications with capability of interfacing to a 5V signal
Package Number
:
(Preliminary)
series resistor in the output helps
BGA54A
MS48A
MTD48
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
DS500443
Features
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to V
resistor is determined by the current-sourcing capability of the driver.
5V tolerant inputs and outputs
2.3V–3.6V V
Equivalent 26
6.2 ns t
Power down high impedance inputs and outputs
Supports live insertion/withdrawal (Note 1)
r
Implements patented noise/EMI reduction circuitry
Latch-up performance exceeds 500 mA
ESD performance:
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
12 mA output drive (V
Human body model
Machine model
Package Description
PD
max (V
CC
CC
:
through a pull-up resistor: the minimum value or the
specifications provided
series resistor outputs
CC
!
200V
!
3.3V), 20
CC
2000V
3.0V)
February 2001
Revised May 2005
P
A I
CC
www.fairchildsemi.com
max

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74lcx162373 Summary of contents

Page 1

... REEL] 74LCX162373MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide (Note 3) 74LCX162373MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide (Note 3) Note 2: BGA package available in Tape and Reel only. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

Page 2

Connection Diagrams Pin Assignment for SSOP and TSSOP Pin Assignment for FBGA (Top Thru View) www.fairchildsemi.com Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW Latch Enable Input n I –I Inputs –O ...

Page 3

Functional Description The LCX162373 contains sixteen D-type latches with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following ...

Page 4

Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Source/Sink Current Supply ...

Page 5

DC Electrical Characteristics Symbol Parameter I Power-Off Leakage Current OFF I Quiescent Supply Current Increase in I per Input CC CC Note 7: Outputs disabled or 3-STATE only. AC Electrical Characteristics Symbol Parameter t Propagation Delay PHL ...

Page 6

AC LOADING and WAVEFORMS FIGURE 1. AC Test Circuit (C Test t PLH t PZL t PZH Waveform for Inverting and Non-Inverting Functions Propagation Delay. Pulse Width and t rec 3-STATE Output Low Enable and Disable Times for Logic (Input ...

Page 7

Schematic Diagram Generic for LCX Family 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide www.fairchildsemi.com Package Number BGA54A Preliminary 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 9 www.fairchildsemi.com ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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