74lcx16500 Fairchild Semiconductor, 74lcx16500 Datasheet

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74lcx16500

Manufacturer Part Number
74lcx16500
Description
74lcx16500 Low Voltage 18-bit Universal Bus Transceivers With 5v Tolerant Inputs And Outputs
Manufacturer
Fairchild Semiconductor
Datasheet
1.74LCX16500.pdf (10 pages)

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Part Number:
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© 2002 Fairchild Semiconductor Corporation
74LCX16500G
(Note 2)(Note 3)
74LCX16500MEA
(Note 3)
74LCX16500MTD
(Note 3)
74LCX16500
Low Voltage 18-Bit Universal Bus Transceivers with
5V Tolerant Inputs and Outputs
General Description
These 18-bit universal bus transceivers combine D-type
latches and D-type flip-flops to allow data flow in transpar-
ent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs.
The LCX16500 is designed for low voltage (2.5V or 3.3V)
V
signal environment.
The LCX16500 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power.
Ordering Code:
Note 2: Ordering code “G” indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Order Number
CC
applications with the capability of interfacing to a 5V
Package Number
BGA54A
MS56A
MTD56
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
DS012407
Features
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to V
value or the resistor is determined by the current-sourcing capability of the
driver.
5V tolerant inputs and outputs
2.3V–3.6V V
6.0 ns t
Power down high impedance inputs and outputs
Supports live insertion/withdrawal (Note 1)
Uses patented noise/EMI reduction circuitry
Latch-up performance exceeds 500 mA
ESD performance:
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
24 mA output drive (V
Human body model
Machine model
Package Description
PD
max (V
CC
CC
and OE tied to GND through a resistor: the minimum
specifications provided
CC
200V
3.3V), 20 A I
CC
2000V
3.0V)
March 1995
Revised June 2002
CC
www.fairchildsemi.com
max

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74lcx16500 Summary of contents

Page 1

... Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide MS56A (Note 3) 74LCX16500MTD 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide MTD56 (Note 3) Note 2: Ordering code “G” indicates Trays. Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. ...

Page 2

Connection Diagrams Pin Assignment for SSOP and TSSOP Pin Assignment for FBGA (Top Thru View) www.fairchildsemi.com Pin Descriptions Pin Names Description Data Register A Inputs/3-STATE Outputs Data Register B Inputs/3-STATE Outputs 1 ...

Page 3

Logic Diagram 3 www.fairchildsemi.com ...

Page 4

Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Source/Sink Current Supply ...

Page 5

DC Electrical Characteristics Symbol Parameter I Quiescent Supply Current CC I Increase in I per Input CC CC Note 10: Outputs disabled or 3-STATE only. AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay PHL t ...

Page 6

AC LOADING and WAVEFORMS FIGURE 1. AC Test Circuit (C t PLH t PZL t PZH Waveform for Inverting and Non-Inverting Functions Propagation Delay. Pulse Width and t rec 3-STATE Output Low Enable and Disable Times for Logic (Input Characteristics; ...

Page 7

Schematic Diagram Generic for LCX Family 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide www.fairchildsemi.com Package Number BGA54A 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS56A 9 www.fairchildsemi.com ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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