74abt240cmsax-nl Fairchild Semiconductor, 74abt240cmsax-nl Datasheet

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74abt240cmsax-nl

Manufacturer Part Number
74abt240cmsax-nl
Description
74abt240 Octal Buffer/line Driver With 3-state Outputs
Manufacturer
Fairchild Semiconductor
Datasheet
© 2005 Fairchild Semiconductor Corporation
74ABT240CSC
74ABT240CSJ
74ABT240CMSA
74ABT240CMTC
74ABT240
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The ABT240 is an inverting octal buffer and line driver
designed to be employed as a memory address driver,
clock driver and bus oriented transmitter or receiver which
provides improved PC board density.
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Order Number
Package Number
MSA20
MTC20
M20D
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
DS011664
Features
Pin Descriptions
Truth Tables
H
L
X
Z
OE
I
O
0
Output sink capability of 64 mA, source capability of
32 mA
Guaranteed latchup protection
High impedance glitch free bus loading during entire
power up and power down cycle
Nondestructive hot insertion capability
–I
0
LOW Voltage Level
Immaterial
High Impedance
HIGH Voltage Level
–O
1
7
, OE
Pin Names
OE
OE
7
Package Description
H
H
L
L
L
L
2
1
2
Inputs
Inputs
I
I
H
X
H
X
L
L
n
n
3-STATE Output
Enable Inputs
Inputs
Outputs
March 1994
Revised March 2005
Description
(Pins 12, 14, 16, 18)
(Pins 3, 5, 7, 9)
www.fairchildsemi.com
Outputs
Outputs
H
H
L
Z
L
Z

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74abt240cmsax-nl Summary of contents

Page 1

... Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Connection Diagram © 2005 Fairchild Semiconductor Corporation Features Output sink capability of 64 mA, source capability ...

Page 2

Absolute Maximum Ratings Storage Temperature Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 2)  Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State ...

Page 3

AC Electrical Characteristics Symbol Parameter Min t Propagation Delay PLH t Data to Outputs PHL t Output Enable PZH t Time PZL t Output Disable PHZ t Time PLZ Capacitance Symbol Parameter C Input Capacitance IN C (Note 5) Output ...

Page 4

AC Loading *Includes jig and probe capacitance Standard AC Test Load Amplitude 3.0V Test Input Signal Requirements AC Waveforms Propagation Delay, Pulse Width Waveforms 3-STATE Output HIGH and LOW Enable and Disable Times www.fairchildsemi.com Test Input Signal Levels Rep. Rate ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M20D 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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