dm74als169b Fairchild Semiconductor, dm74als169b Datasheet

dm74als169b

Manufacturer Part Number

dm74als169b

Description

Synchronous Four-bit Up/down Counters

Manufacturer

Fairchild Semiconductor

Datasheet

1.DM74ALS169B.pdf (7 pages)

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DM74ALS169BM

DM74ALS169BN

DM74ALS169B

Synchronous Four-Bit Up/Down Counters

General Description

These synchronous presettable counters feature an inter-

nal carry look ahead for cascading in high speed counting

applications. The DM74ALS169B is a four-bit binary up/

down counter. The carry output is decoded to prevent

spikes during normal mode of counting operation. Synchro-

nous operation is provided so that outputs change coinci-

dent with each other when so instructed by count enable

inputs and internal gating. This mode of operation elimi-

nates the output counting spikes which are normally asso-

ciated with asynchronous (ripple clock) counters. A

buffered clock input triggers the four flip-flops on the rising

(positive going) edge of clock input waveform.

These counters are fully programmable; that is, the outputs

may each be preset either HIGH or LOW. The load input

circuitry allows loading with carry-enable output of cas-

caded counters. As loading is synchronous, setting up a

low level at the load input disables the counter and causes

the outputs to agree with the data inputs after the next

clock pulse.

The carry look-ahead circuitry permits cascading counters

for n-bit synchronous applications without additional gating.

Both count enable inputs (P and T) must be LOW to count.

The direction of the count is determined by the level of the

up/down input. When the input is HIGH, the counter counts

UP; when LOW, it counts DOWN. Input T is fed forward to

enable the carry outputs. The carry output thus enabled will

produce a low level output pulse with a duration approxi-

mately equal to the high portion of the Q

counting UP, and approximately equal to the low portion of

the Q

pulse can be used to enable successively cascaded

stages. Transitions at the enable P or T inputs are allowed

regardless of the level of the clock input.

The control functions for these counters are fully synchro-

nous. Changes at control inputs (enable P, enable T, load,

up/down) which modify the operating mode have no effect

until clocking occurs. The function of the counter (whether

enabled, disabled, loading or counting) will be dictated

solely by the conditions meeting the stable setup and hold

times.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Order Number

when counting DOWN. This low level overflow carry

Package Number

M16A

N16E

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

output when

DS006207

Features

Switching specifications at 50 pF

Switching specifications guaranteed over full tempera-

ture and V

Advanced oxide-isolated, ion-implanted Schottky TTL

process

Functionally and pin-for-pin compatible with Schottky

and low power Schottky TTL counterpart

Improved AC performance over Schottky and low power

Schottky counterparts

Synchronously programmable

Internal look ahead for fast counting

Carry output for n-bit cascading

Synchronous counting

ESD inputs

Package Description

range

April 1984

Revised April 2000

www.fairchildsemi.com

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dm74als169b Summary of contents

Page 1

... General Description These synchronous presettable counters feature an inter- nal carry look ahead for cascading in high speed counting applications. The DM74ALS169B is a four-bit binary up/ down counter. The carry output is decoded to prevent spikes during normal mode of counting operation. Synchro- nous operation is provided so that outputs change coinci- dent with each other when so instructed by count enable inputs and internal gating ...

Page 2

Connection Diagram Mode Select Table LOAD State Diagram www.fairchildsemi.com Action on Rising ET U/D Clock Edge X X Load ( Count Up (Increment) ...

Page 3

Logic Diagram 3 www.fairchildsemi.com ...

Page 4

Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Typical JA N Package M Package Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input ...

Page 5

Electrical Characteristics over recommended operating free air temperature range. All typical values are measured at V Symbol Parameter V Input Clamp Voltage HIGH Level Output Voltage V V LOW Level OL V Output Voltage ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow www.fairchildsemi.com Package Number M16A 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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