dm74ls165 Fairchild Semiconductor, dm74ls165 Datasheet

dm74ls165

Manufacturer Part Number

dm74ls165

Description

8-bit Parallel In/serial Output Shift Registers

Manufacturer

Fairchild Semiconductor

Datasheet

1.DM74LS165.pdf (6 pages)

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DM74LS165M

DM74LS165WM

DM74LS165N

DM74LS165

8-Bit Parallel In/Serial Output Shift Registers

General Description

This device is an 8-bit serial shift register which shifts data

in the direction of Q

access is made available by eight individual direct data

inputs, which are enabled by a low level at the shift/load

input. These registers also feature gated clock inputs and

complementary outputs from the eighth bit.

Clocking is accomplished through a 2-input NOR gate, per-

mitting one input to be used as a clock-inhibit function.

Holding either of the clock inputs HIGH inhibits clocking,

and holding either clock input LOW with the load input

HIGH enables the other clock input. The clock-inhibit input

should be changed to the high level only while the clock

input is HIGH. Parallel loading is inhibited as long as the

load input is HIGH. Data at the parallel inputs are loaded

directly into the register on a HIGH-to-LOW transition of the

shift/load input, regardless of the logic levels on the clock,

clock inhibit, or serial inputs.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Order Number

Package Number

toward Q

M16A

M16B

N16E

when clocked. Parallel-in

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

DS006399

Features

Function Table

a...h

Shift/ Clock Clock Serial Parallel Outputs Output

Load Inhibit

indicated steady-state input conditions were established.

Complementary outputs

Direct overriding (data) inputs

Gated clock inputs

Parallel-to-serial data conversion

Typical frequency 35 MHz

Typical power dissipation 105 mW

LOW Level (steady state)

Transition from LOW-to-HIGH level

Don't Care (any input, including transitions)

, Q

HIGH Level (steady state)

transition of the clock.

The level of steady-state input at inputs A through H, respectively.

, Q

Package Description

The level of Q

Inputs

or Q

, Q

, respectively, before the most recent

, or Q

August 1986

Revised March 2000

A...H

a...h

, respectively, before the

www.fairchildsemi.com

Internal

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dm74ls165 Summary of contents

Page 1

... Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS165WM M16B 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS165N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

Page 2

Logic Diagram Timing Diagram Typical Shift, Load, and Inhibit Sequences www.fairchildsemi.com 2 ...

Page 3

Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input Voltage IL I HIGH Level Output ...

Page 4

Switching Characteristics and Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay Time PLH LOW-to-HIGH Level Output t Propagation Delay Time PHL HIGH-to-LOW Level Output t Propagation Delay Time PLH LOW-to-HIGH ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M16A Package Number M16B 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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