dm74ls170wm Fairchild Semiconductor, dm74ls170wm Datasheet

dm74ls170wm

Manufacturer Part Number

dm74ls170wm

Description

3-state 4-by-4 Register File

Manufacturer

Fairchild Semiconductor

Datasheet

1.DM74LS170WM.pdf (6 pages)

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DM74LS670M

DM74LS670N

DM74LS670

3-STATE 4-by-4 Register File

General Description

These register files are organized as 4 words of 4 bits

each, and separate on-chip decoding is provided for

addressing the four word locations to either write-in or

retrieve data. This permits writing into one location, and

reading from another word location, simultaneously.

Four data inputs are available to supply the word to be

stored. Location of the word is determined by the write

select inputs A and B, in conjunction with a write-enable

signal. Data applied at the inputs should be in its true form.

That is, if a high level signal is desired from the output, a

high level is applied at the data input for that particular bit

location. The latch inputs are arranged so that new data

will be accepted only if both internal address gate inputs

are HIGH. When this condition exists, data at the D input is

transferred to the latch output. When the write-enable

input, G

levels can cause no change in the information stored in the

internal latches. When the read-enable input, G

the data outputs are inhibited and go into the high imped-

ance state.

The individual address lines permit direct acquisition of

data stored in any four of the latches. Four individual

decoding gates are used to complete the address for read-

ing a word. When the read address is made in conjunction

with the read-enable signal, the word appears at the four

outputs.

This arrangement—data entry addressing separate from

data read addressing and individual sense line — elimi-

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Order Number

, is HIGH, the data inputs are inhibited and their

Package Number

M16A

N16E

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

DS006436

, is HIGH,

nates recovery times, permits simultaneous reading and

writing, and is limited in speed only by the write time (27 ns

typical) and the read time (24 ns typical). The register file

has a non-volatile readout in that data is not lost when

addressed.

All inputs (except read enable and write enable) are buff-

ered to lower the drive requirements to one normal Series

DM74LS load, and input clamping diodes minimize switch-

ing transients to simplify system design. High speed, dou-

ble ended AND-OR-INVERT gates are employed for the

read-address function and have high sink current, 3-STATE

outputs. Up to 128 of these outputs may be wire-AND con-

nected for increasing the capacity up to 512 words. Any

number of these registers may be paralleled to provide n-

bit word length.

Features

For use as:

Separate read/write addressing permits simultaneous

reading and writing

Organized as 4 words of 4 bits

Expandable to 512 words of n-bits

3-STATE versions of DM74LS170

Fast access times 20 ns typ

Scratch pad memory

Buffer storage between processors

Bit storage in fast multiplication designs

Package Description

August 1986

Revised March 2000

www.fairchildsemi.com

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dm74ls170wm Summary of contents

Page 1

... Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2000 Fairchild Semiconductor Corporation nates recovery times, permits simultaneous reading and writing, and is limited in speed only by the write time (27 ns typical) and the read time (24 ns typical) ...

Page 2

Connection Diagram Function Tables Write Table (Note 1)(Note 2) Write Inputs Word ...

Page 3

Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input Voltage IL I HIGH Level Output ...

Page 4

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter V Input Clamp Voltage I V HIGH Level OH Output Voltage V LOW Level OL Output Voltage I Input Current @ Max I Input Voltage I ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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