m36w832te STMicroelectronics, m36w832te Datasheet
m36w832te
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m36w832te Summary of contents
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... PPF ACCESS TIMES: 70ns and 85ns LOW POWER CONSUMPTION ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Top Device Code, M36W832TE: 88BAh – Bottom Device Code, M36W832BE: 88BBh FLASH MEMORY 32 Mbit (2Mb x16) BOOT BLOCK – KWord Parameter Blocks (Top or Bottom Location) PROGRAMMING TIME – ...
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... M36W832TE, M36W832BE TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. LFBGA Connections (Top view through package Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Address Inputs (A0-A18 Address Inputs (A19-A20 Data Input/Output (DQ0-DQ15 Flash Chip Enable (EF Flash Output Enable (GF Flash Write Enable (WF Flash Write Protect (WPF) ...
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... Program Status (Bit 4 Status (Bit PPF Program Suspend Status (Bit Block Protection Status (Bit Reserved (Bit Table 11. Flash Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SRAM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 MAXIMUM RATING Table 12. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 M36W832TE, M36W832BE 3/64 ...
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... PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 25. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 APPENDIX A. FLASH MEMORY BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 26. Top Boot Block Addresses, M36W832TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 27. Bottom Boot Block Addresses, M36W832BE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 APPENDIX B. COMMON FLASH INTERFACE (CFI Table 28. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 29. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 30 ...
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... Figure 33. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 60 APPENDIX D. FLASH MEMORY COMMAND INTERFACE and PROGRAM/ERASE CONTROLLER STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 34. Write State Machine Current/Next, sheet Table 35. Write State Machine Current/Next, sheet REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 36. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 M36W832TE, M36W832BE 5/64 ...
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... M36W832TE, M36W832BE SUMMARY DESCRIPTION The M36W832TE is a low voltage Multiple Memo- ry Product which combines two memory devices Mbit boot block Flash memory and an 8 Mbit SRAM. Recommended operating conditions do not allow both the Flash and the SRAM to be ac- tive at the same time. ...
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... Figure 3. LFBGA Connections (Top view through package) M36W832TE, M36W832BE 7/64 ...
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... M36W832TE, M36W832BE Signal Descriptions See Figure 2 Logic Diagram and Table 1,Signal Names, for a brief overview of the signals connect this device. Address Inputs (A0-A18). Addresses are common inputs for the Flash and the SRAM components. The Address Inputs select the cells in the memory array to access during Bus Read operations ...
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... Therefore it is recommended to put the SRAM in the high impedance state when reading the Flash and vice versa (see Table 2 Main Oper- ation Modes for details). V DDQF V DDF V PPF Flash Memory 32 Mbit (x16) V SSF V DDS SRAM 8 Mbit (x16) V SSS M36W832TE, M36W832BE DQ0-DQ15 AI90163 9/64 ...
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... M36W832TE, M36W832BE Table 2. Main Operation Modes Operation RPF WPF Mode Read Write Block Locking V V Standby Reset Output Disable Read Flash must be disabled ...
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... The device features an asymmetrical blocked ar- chitecture with an array of 71 blocks: 8 Parameter Blocks of 4 KWords and 63 Main Blocks of 32 KWords. The M36W832TE has the Parameter Blocks at the top of the memory address space while the M36W832BE locates the Parameter Blocks starting from the bottom. The memory maps are shown in Figure 5, Block Addresses ...
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... M36W832TE, M36W832BE Figure 6. Flash Security Block and Protection Register Memory Map 8Ch 85h 84h 81h 80h Note: 1. Bit 2 of the Protection Register Lock must not be programmed to 0. 12/64 PROTECTION REGISTER User Programmable OTP Unique device number (1) Protection Register Lock AI90165b ...
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... The memory operations can be performed using a single low voltage supply, 2.7V to 3.3V, which is the same as the Flash voltage supply. DATA IN DRIVERS 512Kb x 16 RAM Array 2048 x 4096 COLUMN DECODER A11-A18 POWER-DOWN CIRCUIT M36W832TE, M36W832BE DQ0-DQ7 DQ8-DQ15 UBS WS E2S E1S GS LBS E2S E1S UBS ...
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... M36W832TE, M36W832BE OPERATING MODES Flash Bus Operations There are six standard bus operations that control the device. These are Bus Read, Bus Write, Out- put Disable, Standby, Automatic Standby and Re- set. See Table 2, Main Operation Modes, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations ...
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... Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write cycles are required to issue the command. The first bus cycle sets up the Erase command. M36W832TE, M36W832BE Read Status 15/64 ...
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... M36W832TE, M36W832BE The second latches the block address in the internal state machine and starts the Program/ Erase Controller. If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits b4 and b5 are set and the command aborts. Erase aborts if Reset turns to V ...
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... Protection Lock Register (see Figure 6, Flash Security Block and Protection Register Memory Map). Attempting to program a previously protected Protection Register will result in a Status M36W832TE, M36W832BE Register error. The protection of the Protection Register is not reversible. The Protection Register Program cannot be sus- pended ...
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... M36W832TE, M36W832BE Refer to the “Flash Block Locking” section for a de- tailed explanation. Table 4. Flash Commands Commands 1st Cycle Op. Add Data Read Memory 1+ Write X FFh Array Read Status 1+ Write X 70h Register Read Electronic 1+ Write X 90h Signature Read CFI Query 1+ Write X 98h ...
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... ID data Don’t Care OTP data OTP data Don’t Care OTP data OTP data Don’t Care OTP data OTP data Don’t Care OTP data OTP data M36W832TE, M36W832BE A12-A20 DQ0-DQ7 DQ8-DQ15 20h 00h BAh 88h IL V BBh ...
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... M36W832TE, M36W832BE Table 8. Flash Program, Erase Times and Program/Erase Endurance Cycles Parameter Word Program Double Word Program Quadruple Word Program Main Block Program Parameter Block Program Main Block Erase Parameter Block Erase Program/Erase Cycles (per Block) Note: 1. Typical time to program a Main or Parameter Block using the Double Word Program and the Quadruple Word Program commands respectively ...
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... Locked state after a hardware reset or when the device is powered- down. The status of an unlocked block can be changed to Locked or Locked-Down using the ap- M36W832TE, M36W832BE propriate software commands. A locked block can be unlocked by issuing the Unlock command. Lock-Down State. Blocks that are Locked-Down ...
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... M36W832TE, M36W832BE Table 9. Block Lock Status Item Block Lock Configuration Block is Unlocked Block is Locked Block is Locked-Down Table 10. Protection Status Current (1) Lock Status (WPF, DQ1, DQ0) Program/Erase Current State Allowed 1,0,0 yes (2) no 1,0,1 1,1,0 yes 1,1,1 no 0,0,0 yes (2) no 0,0,1 0,1,1 no Note: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read in the Read Electronic Signature command with ...
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... Suspend mode. M36W832TE, M36W832BE When a Program/Erase Resume command is is- sued the Erase Suspend Status bit returns Low. Erase Status (Bit 5). The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly ...
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... M36W832TE, M36W832BE gram/Erase Controller Status bit is High (Program/ Erase Controller inactive). Bit 2 is set within 5µs of the Program/Erase Suspend command being is- sued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is is- sued the Program Suspend Status bit returns Low ...
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... Controlled and SRAM Low V AC Waveforms, E2S Controlled, respectively. . Either IH Output Disable. The data outputs are high im- pedance when the Output Enable, GS with Write Enable, WS M36W832TE, M36W832BE and The data is latched IL , E2S its falling edge. Care ...
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... M36W832TE, M36W832BE MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause per- manent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- Table 12 ...
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... Input Capacitance IN C Output Capacitance OUT Note: Sampled only, not 100% tested. M36W832TE, M36W832BE in their circuit match the measurement conditions when relying on the quoted parameters. The operating and AC measurement parameters given below (see Table 13, Operating and AC Measurement Conditions) are those of the stand- alone Flash and SRAM devices and some differ from those of the stacked product ...
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... M36W832TE, M36W832BE Table 15. DC Characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current Standby Current DDS DD Supply Current I DDD (Reset) I Supply Current DD Supply Current I DDR (Read) Supply Current I DDW (Program) Supply Current I DDE (Erase) Supply Current I (Program/Erase DDES Suspend) ...
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... DDQF DDS SRAM min Flash & DDQF DDS DD SRAM I = 100µ min Flash & DDQF DDS DD SRAM I = –100µA OH Flash Flash Flash Flash M36W832TE, M36W832BE Min Typ Max Unit µA –0.3 0 DDQF V +0.4 QF 0.1 V 2.4 V 1.65 3.6 V 11.4 12 ...
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... M36W832TE, M36W832BE Figure 10. Flash Read Mode AC Waveforms A0-A20 EF GF DQ0-DQ15 ADDR. VALID CHIP ENABLE Table 16. Flash Read AC Characteristics Symbol Alt t t Address Valid to Next Address Valid AVAV Address Valid to Output Valid AVQV ACC (1) t Address Transition to Output Transition t OH AXQX ...
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... Figure 11. Flash Write AC Waveforms, Write Enable Controlled M36W832TE, M36W832BE 31/64 ...
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... M36W832TE, M36W832BE Table 17. Flash Write AC Characteristics, Write Enable Controlled Symbol Alt t t Write Cycle Time AVAV Address Valid to Write Enable High AVWH Data Valid to Write Enable High DVWH Chip Enable Low to Write Enable Low ELWL CS t Chip Enable Low to Output Valid ...
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... Figure 12. Flash Write AC Waveforms, Chip Enable Controlled M36W832TE, M36W832BE 33/64 ...
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... M36W832TE, M36W832BE Table 18. Flash Write AC Characteristics, Chip Enable Controlled Symbol Alt t t Write Cycle Time AVAV Address Valid to Chip Enable High AVEH Data Valid to Chip Enable High DVEH Chip Enable High to Address Transition EHAX Chip Enable High to Data Transition ...
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... Sampled only, not 100% tested important to assert RPF in order to allow proper CPU initialization during power up or reset. tPHWL tPHEL tPHGL Reset Test Condition During Program and Erase others < 100ns. PLPH M36W832TE, M36W832BE tPHWL tPHEL tPHGL tPLPH AI90171 Flash Device Unit 70 85 Min 50 50 µ ...
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... M36W832TE, M36W832BE Figure 14. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = V A0-A18 DQ0-DQ15 DATA VALID Note: E1S = Low, E2S = High Low High. Figure 15. SRAM Read AC Waveforms, GS Controlled A0-A18 E1S E2S GS DQ0-DQ15 tPU V DDS Note: Write Enable (WS) = High. Address Valid prior the same time as E1S goes Low and E2S goes High. ...
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... If E1S or E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance. Parameter or E2S Controlled S tAVAV ADDRESS VALID tAVE1H tAVE2L tAVE1L tE1LE1H tAVE2H tE2HE2L tWLE1H tWLE2L tDVE1H tDVE2L INPUT VALID . IH M36W832TE, M36W832BE SRAM Unit Min Max ...
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... M36W832TE, M36W832BE Figure 18. SRAM Write AC Waveforms, WS Controlled, GS High during Write A0-A18 E1S E2S WS GS tGHQZ DQ0-DQ15 Note: 1. DQ0-DQ15 are high impedance E1S or E2s and WS are deasserted at the same time, DQ0-DQ15 remain high impedance. Figure 19. SRAM Write AC Waveforms, WS Controlled with GS Low ...
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... Figure 20. SRAM Write Cycle Waveform, UBS and LBS Controlled GS Low, A0-A18 E1S E2S UBS, LBS tAVWL WS tWLQZ DQ0-DQ15 Note 1 Note: 1. During this period, the I/O pins are in output mode and input signals should not be applied. M36W832TE, M36W832BE tAVAV VALID tAVBH tBLBH tDVBH tBHDZ INPUT VALID tBHAX tBHQX AI07969 ...
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... M36W832TE, M36W832BE Table 21. SRAM Write AC Characteristics Symbol Alt t t Write Cycle Time AVAV AVE1L Address Valid to Beginning of Write AVE2H AS t AVWL AVE1H Address Valid to Chip Enable 1 Low or Chip Enable AVE2L AW High t AVBH t t Address Valid to Write Enable High ...
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... E2S < 0.3V DDS or E2S > 0.3V DDS DATA RETENTION MODE V DR > 1.5V tCDR E2S < 0.3V Test Condition V = 1.5V, E1S V DDS DDS V V – 0. DDS IN No input may exceed V DDS M36W832TE, M36W832BE V DDS (min) tR AI07970 V DDS (min) tR AI07982 Min Typ Max – 0.3V, 0. 0.3V 1.5 3 Unit µA ...
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... M36W832TE, M36W832BE PACKAGE MECHANICAL Figure 23. Stacked LFBGA66 12x8mm, 8x8 array, 0.8mm pitch, Bottom View Package Outline BALL "A1" Note: Drawing is not to scale. Table 23. Stacked LFBGA66, 12x8mm, 8x8 ball array, 0.8mm pitch, Package Mechanical Data millimeters Symbol Typ A A1 ...
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... Figure 24. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package) M36W832TE, M36W832BE 43/64 ...
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... M36W832TE, M36W832BE Figure 25. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package) 44/64 ...
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... LFBGA66: 12x8mm, 0.8mm pitch Option T = Tape & Reel Packing For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. M36 W 8 32T 2.7V to 3.3V M36W832TE -ZA T M36W832TE, M36W832BE 6 T 45/64 ...
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... M36W832TE, M36W832BE APPENDIX A. FLASH MEMORY BLOCK ADDRESS TABLES Table 26. Top Boot Block Addresses, M36W832TE Size # Address Range (KWord 1FF000-1FFFFF 1 4 1FE000-1FEFFF 2 4 1FD000-1FDFFF 3 4 1FC000-1FCFFF 4 4 1FB000-1FBFFF 5 4 1FA000-1FAFFF 6 4 1F9000-1F9FFF 7 4 1F8000-1F8FFF 8 32 1F0000-1F7FFF 9 32 1E8000-1EFFFF 10 32 1E0000-1E7FFF 11 32 ...
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... M36W832TE, M36W832BE 36 32 0E8000-0EFFFF 35 32 0E0000-0E7FFF 34 32 0D8000-0DFFFF 33 32 0D0000-0D7FFF 32 32 0C8000-0CFFFF 31 32 0C0000-0C7FFF 30 32 0B8000-0BFFFF 29 32 0B0000-0B7FFF 28 32 0A8000-0AFFFF 27 32 ...
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... M36W832TE, M36W832BE APPENDIX B. COMMON FLASH INTERFACE (CFI) The Common Flash Interface is a JEDEC ap- proved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory ...
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... HEX value in volts bit BCD value in 100 mV bit HEX value in volts bit BCD value in 100 mV n µ times typical n n times typical M36W832TE, M36W832BE Value 2.7V 3.6V 11.4V 12.6V 16µs n 16µs µ 512µs n 512µs times typical 8s times typical ...
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... M36W832TE, M36W832BE Table 31. Device Geometry Definition Offset Word Data Mode 27h 0016h Device Size = 2 28h 0001h Flash Device Interface Code description 29h 0000h 2Ah 0003h Maximum number of bytes in multi-byte program or page = 2 2Bh 0000h Number of Erase Block Regions within the device. 2Ch ...
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... Lock/bytes JEDEC-plane physical low address Lock/bytes JEDEC-plane physical high address n "n" such that 2 = factory pre-programmed bytes n "n" such that 2 = user programmable bytes M36W832TE, M36W832BE Value "P" "R" "I" "1" "0" Yes No Yes No) ...
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... M36W832TE, M36W832BE Table 33. Security Code Area Offset Data 80h 00XX Protection Register Lock 81h XXXX 82h XXXX 64 bits: unique device number 83h XXXX 84h XXXX 85h XXXX 86h XXXX 87h XXXX 88h XXXX 128 bits: User Programmable OTP 89h XXXX 8Ah ...
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... Program Command status_register=readFlash (any_address must be toggled*/ } while (status_register.b7 (status_register.b3==1) /*V PPF invalid error */ error_handler ( ) ; if (status_register.b4==1) /*program error */ error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; } Invalid) and b4 (Program Error) can be made after each program operation or after PPF M36W832TE, M36W832BE AI90174b 53/64 ...
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... M36W832TE, M36W832BE Figure 27. Double Word Program Flowchart and Pseudo Code Start Write 30h Write Address 1 & Data 1 (3) Write Address 2 & Data 2 (3) Read Status Register YES YES YES NO Program to Protected Block Error (1, 2) YES End Note: 1. Status check of b1 (Protected Block sequence ...
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... PPF invalid error */ error_handler ( ) ; if (status_register.b4==1) /*program error */ error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; } Invalid) and b4 (Program Error) can be made after each program operation or after PPF M36W832TE, M36W832BE addressToProgram2, dataToProgram2, addressToProgram3, dataToProgram3, addressToProgram4, dataToProgram4) /*see note (3) */ /*see note (3) */ /*see note (3) */ /*see note (3) */ AI07950 ...
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... M36W832TE, M36W832BE Figure 29. Program Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register YES YES Write FFh Read data from another address Write D0h Program Continues 56/64 program_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (any_address, 0x70) ; ...
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... Erase Command */ do { status_register=readFlash (any_address must be toggled*/ } while (status_register.b7 PPF Invalid if (status_register.b3==1) /*V PPF invalid error */ Error (1) error_handler ( ) ; if ( (status_register.b4==1) && (status_register.b5==1) ) Command /* command sequence error */ error_handler ( ) ; if ( (status_register.b5== erase error */ error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; } M36W832TE, M36W832BE AI90177b 57/64 ...
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... M36W832TE, M36W832BE Figure 31. Erase Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register YES YES Write FFh Read data from another block or Program/Protection Program or Block Protect/Unprotect/Lock Write D0h Erase Continues 58/64 erase_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; ...
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... Register NO Locking change confirmed? YES Write FFh End M36W832TE, M36W832BE locking_operation_command (address, lock_operation) { writeToFlash (any_address, 0x60) ; /*configuration setup*/ if (lock_operation==PROTECT) /*to protect the block*/ writeToFlash (address, 0x01) ; else if (lock_operation==UNPROTECT) /*to unprotect the block*/ writeToFlash (address, 0xD0) ; else if (lock_operation==LOCK) /*to lock the block*/ writeToFlash (address, 0x2F) ...
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... M36W832TE, M36W832BE Figure 33. Protection Register Program Flowchart and Pseudo Code Start Write C0h Write Address & Data Read Status Register YES NO V PPF Invalid YES YES NO Program to Protected Block Error (1, 2) YES End Note: 1. Status check of b1 (Protected Block sequence ...
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... Read Array Program Erase Sus Erase Erase Sus Setup Read Array (continue) Read Array Program Erase Read Array Setup Setup M36W832TE, M36W832BE Prog/Ers Read Clear Resume Status Status (D0h) (70h) (50h) Read Sts. Read Array Read Read Array Status Read ...
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... M36W832TE, M36W832BE Table 35. Write State Machine Current/Next, sheet Read CFI Current State Read Elect.Sg. Query (90h) (98h) Read Array Read Elect.Sg. Read CFI Query Read Status Read Elect.Sg. Read CFI Query Read Elect.Sg. Read Elect.Sg. Read CFI Query Read CFI Query Read Elect.Sg. Read CFI Query ...
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... Diagram. Input Rise and Fall Time for 70ns speed class modified in Operating and AC 24-Mar-2003 3.0 Measurement Conditions Table. LFBGA Connections and Daisy Chain pin numbers modified. 26-May-2003 3.1 Special tape option added to ordering information scheme M36W832TE, M36W832BE Revision Details Maximum changed to 3.6V, Corrections to Table 8, Flash DDQF 63/64 ...
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... M36W832TE, M36W832BE Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...