hyb39s256400 Infineon Technologies Corporation, hyb39s256400 Datasheet - Page 10

• Manufacturer Part Number: hyb39s256400
• Description: 256 Mbit Synchronous Dram
• Manufacturer: Infineon Technologies Corporation

Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the truth table for the operation commands.
Operation
Bank Active
Bank Precharge
Precharge All
Write
Write with Autoprecharge
Read
Read with Autoprecharge
Mode Register Set
No Operation
Burst Stop
Device Deselect
Auto Refresh
Self Refresh Entry
Self Refresh Exit
Clock Suspend Entry
Power Down Entry
(Precharge or active
standby)
Clock Suspend Exit
Power Down Exit
Data Write/Output Enable
Data Write/Output Disable Active
INFINEON Technologies
Notes
1. V = Valid, x = Don’t Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the
3. This is the state of the banks designated by BA0, BA1 signals.
4. Power Down Mode can not be entered in a burst cycle. When this command asserted in the burst mode cycle
commands are provided.
device is in clock suspend mode.
Device
State
Idle
Any
Any
Active
Active
Active
Active
Idle
Any
Active
Any
Idle
Idle
Idle
(Self
Refr.)
Active
Idle
Active
Active
Any
(Power
Down)
Active
3
3
3
3
3
4
CKE
n-1
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
CKE
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
X
X
n
L
L
L
DQM
10
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
HYB39S256400/800/160DT(L)/DC(L)
BA0
BA1
V
V
X
V
V
V
V
V
X
X
X
X
X
X
X
X
X
X
X
X
256MBit Synchronous DRAM
AP=
A10
H
H
H
V
L
L
L
V
X
X
X
X
X
X
X
X
X
X
X
X
Addr
V
X
X
V
V
V
V
V
X
X
X
X
X
X
X
X
X
X
X
X
.
CS
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
X
L
X
X
RAS
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
L
L
L
L
L
L
CAS
2002-04-23
H
H
H
H
H
H
H
H
L
L
L
L
L
X
L
L
X
X
X
X
X
X
X
WE
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L