fm93cs56 Fairchild Semiconductor, fm93cs56 Datasheet - Page 5

• Manufacturer Part Number: fm93cs56
• Description: Microwire ? Bus Interface 2048-bit Serial Eeprom With Data Protect And Sequential Read
• Manufacturer: Fairchild Semiconductor

FM93CS56 Rev. C.1
This is an active high input pin to FM93CS56 EEPROM (the device)
and is generated by a master that is controlling the device. A high
level on this pin selects the device and a low level deselects the
device. All serial communications with the device is enabled only
when this pin is held high. However this pin cannot be permanently
tied high, as a rising edge on this signal is required to reset the
internal state-machine to accept a new cycle and a falling edge to
initiate an internal programming after a write cycle. All activity on the
SK, DI and DO pins are ignored while CS is held low.
This is an input pin to the device and is generated by the master that
is controlling the device. This is a clock signal that synchronizes the
communication between a master and the device. All input informa-
tion (DI) to the device is latched on the rising edge of this clock input,
while output data (DO) from the device is driven from the rising edge
of this clock input. This pin is gated by CS signal.
This is an input pin to the device and is generated by the master
that is controlling the device. The master transfers Input informa-
tion (Start bit, Opcode bits, Array addresses and Data) serially via
this pin into the device. This Input information is latched on the
rising edge of the SCK. This pin is gated by CS signal.
This is an output pin from the device and is used to transfer Output
data via this pin to the controlling master. Output data is serially
shifted out on this pin from the rising edge of the SCK. This pin is
active only when the device is selected.
This is an active high input pin to the device and is used to
distinguish operations to memory array and operations to Protect
Register. When this pin is held low, operations to the memory
array are enabled. When this pin is held high, operations to the
Protect Register are enabled. This pin operates in conjunction
with PE pin. Refer Table1 for functional matrix of this pin for
various operations.
Instruction
PRCLEAR
PRWRITE
PRREAD
WRALL
WRITE
READ
PREN
PRDS
WEN
WDS
Start Bit Opcode Field
1
1
1
1
1
1
1
1
1
1
10
00
01
00
00
10
00
11
01
00
X
1
X
0
0
X
1
1
X
0
A6 A5 A4 A3 A2 A1 A0
A6 A5 A4 A3 A2 A1 A0
A6 A5 A4 A3 A2 A1 A0
1
1
0
X
1
1
0
Address Field
X
X
X
X
X
1
0
X
X
X
X
X
1
0
This is an active high input pin to the device and is used to enable
operations, that are write in nature, to the memory array and to the
Protect register. When this pin is held high, operations that are
“write” in nature are enabled. When this pin is held low, operations
that are “write” in nature are disabled. This pin operates in
conjunction with PRE pin. Refer Table1 for functional matrix of this
pin for various operations.
A typical communication on the Microwire bus is made through the
CS, SK, DI and DO signals. To facilitate various operations on the
Memory array and on the Protect Register, a set of 10 instructions
are implemented on FM93CS56. The format of each instruction is
listed in Table 1.
Each of the above 10 instructions is explained under individual
instruction descriptions.
This is a 1-bit field and is the first bit that is clocked into the device
when a Microwire cycle starts. This bit has to be “1” for a valid cycle
to begin. Any number of preceding “0” can be clocked into the
device before clocking a “1”.
This is a 2-bit field and should immediately follow the start bit.
These two bits (along with PRE, PE signals and 2 MSB of address
field) select a particular instruction to be executed.
This is a 8-bit field and should immediately follow the Opcode bits.
In FM93CS56, only the LSB 7 bits are used for address decoding
during READ, WRITE and PRWRITE instructions. During these
three instructions (READ, WRITE and PRWRITE), the MSB is
“don’t care” (can be 0 or 1). During all other instructions (with the
exception of PRREAD), the MSB 2 bits are used to decode
instruction (along with Opcode bits, PRE and PE signals).
This is a 16-bit field and should immediately follow the Address
bits. Only the WRITE and WRALL instructions require this field.
D15 (MSB) is clocked first and D0 (LSB) is clocked last (both
during writes as well as reads).
X
X
X
X
X
1
0
X
X
X
X
X
1
0
X
X
X
X
X
1
0
X
X
X
X
X
1
0
Data Field PRE Pin
D15-D0
D15-D0
0
0
0
0
0
1
1
1
1
1
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PE Pin
X
X
X
1
1
1
1
1
1
1