r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 14

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

Section 7 DMA Controller (DMAC).................................................................307
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Rev. 1.00 Sep. 19, 2008 Page xiv of xxviii
6.15.3 External Bus Release Function and CBR Refreshing/Auto Refreshing................ 305
6.15.4 BREQO Output Timing ........................................................................................ 306
6.15.5 Notes on Usage of the Synchronous DRAM ........................................................ 306
Features.............................................................................................................................. 307
Input/Output Pins............................................................................................................... 309
Register Descriptions ......................................................................................................... 310
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
Activation Sources............................................................................................................. 337
7.4.1
7.4.2
Operation ........................................................................................................................... 339
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10 DMA Transfer (Single Address Mode) Bus Cycles ............................................. 374
7.5.11 Write Data Buffer Function .................................................................................. 380
7.5.12 Multi-Channel Operation...................................................................................... 381
7.5.13 Relation between DMAC and External Bus Requests,
7.5.14 DMAC and NMI Interrupts .................................................................................. 384
7.5.15 Forced Termination of DMAC Operation ............................................................ 385
7.5.16 Clearing Full Address Mode................................................................................. 386
Interrupt Sources................................................................................................................ 387
Usage Notes ....................................................................................................................... 388
Memory Address Registers (MARA and MARB)................................................ 312
I/O Address Registers (IOARA and IOARB)....................................................... 313
Execute Transfer Count Registers (ETCRA and ETCRB) ................................... 313
DMA Control Registers (DMACRA and DMACRB) .......................................... 315
DMA Band Control Registers H and L (DMABCRH and DMABCRL).............. 323
DMA Write Enable Register (DMAWER)........................................................... 334
DMA Terminal Control Register (DMATCR) ..................................................... 336
Activation by Internal Interrupt Request .............................................................. 338
Activation by Auto-Request ................................................................................. 339
Transfer Modes..................................................................................................... 339
Sequential Mode ................................................................................................... 342
Idle Mode.............................................................................................................. 345
Repeat Mode......................................................................................................... 348
Single Address Mode............................................................................................ 352
Normal Mode........................................................................................................ 355
Block Transfer Mode ............................................................................................ 359
Basic Bus Cycles .................................................................................................. 365
DMA Transfer (Dual Address Mode) Bus Cycles................................................ 366
Refresh Cycles, and EXDMAC ............................................................................ 383