r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 81

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

2.4.4
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
Bit
7
6
5
4
3
Condition-Code Register (CCR)
Bit Name
I
UI
H
U
N
Initial Value
1
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
R/W
R/W
Description
Interrupt Mask Bit
Masks interrupts other than NMI when set to 1.
NMI is accepted regardless of the I bit setting.
The I bit is set to 1 by hardware at the start of an
exception-handling sequence. For details, refer
to section 5, Interrupt Controller.
User Bit or Interrupt Mask Bit
Can be written and read by software using the
LDC, STC, ANDC, ORC, and XORC
instructions. This bit cannot be used as an
interrupt mask bit in this LSI.
Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B,
CMP.B, or NEG.B instruction is executed, this
flag is set to 1 if there is a carry or borrow at bit
3, and cleared to 0 otherwise. When the ADD.W,
SUB.W, CMP.W, or NEG.W instruction is
executed, the H flag is set to 1 if there is a carry
or borrow at bit 11, and cleared to 0 otherwise.
When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 27, and cleared
to 0 otherwise.
User Bit
Can be written and read by software using the
LDC, STC, ANDC, ORC, and XORC
instructions.
Negative Flag
Stores the value of the most significant bit of
data as a sign bit.
Rev. 1.00 Sep. 19, 2008 Page 53 of 1270
REJ09B0466-0100
Section 2 CPU