r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 401

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

Figure 7.25 shows an example of block transfer mode transfer activated by DREQ pin low level.
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the dead cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
[1]
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMA cycle is started.
[4] [7] Acceptance is resumed after the dead cycle is completed.
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
φ
DREQ
Address
bus
DMA
control
Channel
Figure 7.25 Example of DREQ Pin Low Level Activated Block Transfer Mode Transfer
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
Idle
Bus release
[1]
Request
of 2 cycles
Minimum
[2]
Read
[3]
Transfer source
Request clear period
DMA
read
Write
1 block transfer
Transfer destination
DMA
write
Acceptance resumes
Dead
[4]
Request
DMA
dead
of 2 cycles
Minimum
Idle
[5]
release
Bus
Read
[6]
Rev. 1.00 Sep. 19, 2008 Page 373 of 1270
Transfer source
Request clear period
DMA
read
Section 7 DMA Controller (DMAC)
Write
1 block transfer
Transfer destination
DMA
write
Dead
Acceptance resumes
REJ09B0466-0100
DMA
dead
[7]
Idle
release
Bus