r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 459

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

(4)
Figure 8.18 shows an example of normal mode transfer activated by the EDREQ pin falling edge.
EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ
pin high level sampling is completed by the end of the DMA write cycle, acceptance resumes after
the end of the write cycle, and EDREQ pin low level sampling is performed again; this sequence
of operations is repeated until the end of the transfer.
Figure 8.19 shows an example of block transfer mode transfer activated by the EDREQ pin falling
edge.
[1]
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] DMA cycle start; EDREQ pin high level sampling is started at rise of φ.
[4], [7] When EDREQ pin high level has been sampled, acceptance is resumed after completion of write cycle.
φ
EDREQ
Address bus
DMA control
Channel
Figure 8.18 Example of Normal Mode Transfer Activated by EDREQ Pin Falling Edge
EDREQ Pin Falling Edge Activation Timing
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.
(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)
Idle
[1]
Minimum 3 cycles
Request
Bus release
[2]
Read
[3]
Request clearance period
Transfer source
DMA read
Write
DMA write
destination
Transfer
Idle
Acceptance
resumed
[4]
Minimum 3 cycles
Request
Bus release
Rev. 1.00 Sep. 19, 2008 Page 431 of 1270
[5]
Section 8 EXDMA Controller (EXDMAC)
Read
[6]
Request clearance period
Transfer source
DMA read
Write
DMA write Bus release
destination
Transfer
REJ09B0466-0100
Idle
Acceptance
resumed
[7]