r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 925

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

As in the above sample start character, with the direct convention type, the logic 1 level
corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order.
The start character data above is H'3B. For the direct convention type, clear the SDIR and SINV
bits in SCMR to 0. According to the Smart Card regulations, clear the O/E bit in SMR to 0 to
select even parity mode.
With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to
state Z, and transfer is performed in MSB-first order. The start character data above is H'3F. For
the inverse convention type, set the SDIR and SINV bits in SCMR to 1. According to the Smart
Card regulations, even parity mode is the logic 0 level of the parity bit, and corresponds to state Z.
In this LSI, the SINV bit inverts only data bits D7 to D0. Therefore, set the O/E bit in SMR to 1 to
invert the parity bit for both transmission and reception.
15.7.3
Operation in block transfer mode is the same as that in normal Smart Card interface, except for the
following points.
• In reception, though the parity check is performed, no error signal is output even if an error is
• In transmission, a guard time of at least 1 etu is left between the end of the parity bit and the
• In transmission, because retransmission is not performed, the TEND flag is set to 1, 11.5 etu
• As with the normal Smart Card interface, the ERS flag indicates the error signal status, but
detected. However, the PER bit in SSR is set to 1 and must be cleared before receiving the
parity bit of the next frame.
start of the next frame.
after transmission start.
since error signal transfer is not performed, this flag is always cleared to 0.
Block Transfer Mode
(Z)
Figure 15.24 Inverse Convention (SDIR = SINV = O/E = 1)
Ds
A
D7 D6 D5 D4 D3 D2 D1 D0 Dp
Z
Z
A
A
A
Section 15 Serial Communication Interface (SCI, IrDA)
A
A
A
Rev. 1.00 Sep. 19, 2008 Page 897 of 1270
Z
(Z) State
REJ09B0466-0100