r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 203

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

6.3.10
DRACCR is used to set the DRAM/synchronous DRAM interface bus specifications.
Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424
Bit
15
14
13
12
11
Group.
Bit Name
DRMI
—
TPC1
TPC0
SDWCD
DRAM Access Control Register (DRACCR)
Initial Value
0
0
0
0
0*
R/W
R/W
R/W
R/W
R/W
R/W
Description
Idle Cycle Insertion
An idle cycle can be inserted after a
DRAM/synchronous DRAM access cycle when a
continuous normal space access cycle follows a
DRAM/synchronous DRAM access cycle. Idle
cycle insertion conditions, setting of number of
states, etc., comply with settings of bits ICIS2,
ICIS1, ICIS0, and IDLC in BCR register
0: Idle cycle not inserted
1: Idle cycle inserted
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
Precharge State Control
These bits select the number of states in the RAS
precharge cycle in normal access and refreshing.
00: 1 state
01: 2 states
10: 3 states
11: 4 states
CAS Latency Control Cycle Disabled during
Continuous Synchronous DRAM Space Write
Access
Disables CAS latency control cycle (Tcl) inserted
by WTCRB (H) settings during synchronous
DRAM write access (see figure 6.5).
0: Enables CAS latency control cycle
1: Disables CAS latency control cycle
Rev. 1.00 Sep. 19, 2008 Page 175 of 1270
Section 6 Bus Controller (BSC)
REJ09B0466-0100