r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 315

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

(7)
(a)
While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after DRAM space access is
disabled. Idle cycle insertion after DRAM space access can be enabled by setting the DRMI bit to
1. The conditions and number of states of the idle cycle to be inserted are in accordance with the
settings of bits ICIS1, ICIS0, and IDLC in BCR are valid. Figures 6.88 and 6.89 show examples of
idle cycle operation when the DRMI bit is set to 1.
When the DRMI bit is cleared to 0, an idle cycle is not inserted after DRAM space access even if
bits ICIS1 and ICIS0 are set to 1.
Idle Cycle in Case of Normal Space Access after DRAM Space Access
Normal space access after DRAM space read access
UCAS, LCAS
Address bus
Data bus
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)
RAS
Figure 6.88 Example of Idle Cycle Operation after DRAM Access
RD
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DRAM space read
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Idle cycle
External address space read
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Rev. 1.00 Sep. 19, 2008 Page 287 of 1270
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Section 6 Bus Controller (BSC)
DRAM space read
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REJ09B0466-0100
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