isppac-powr1220at8 Lattice Semiconductor Corp., isppac-powr1220at8 Datasheet - Page 19

• Manufacturer Part Number: isppac-powr1220at8
• Description: In-system Programmable Power Supply Monitoring, Sequencing And Margining Controller
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Table 1-3. Comparator Hysteresis vs. Trip-Point
The window control section of the voltage monitor circuit is an AND gate (with inputs: an inverted COMPA “ANDed”
with COMPB signal) and a multiplexer that supports the ability to develop a ‘window’ function without using any of
the PLD’s resources. Through the use of the multiplexer, voltage monitor’s ‘A’ output may be set to report either the
status of the ‘A’ comparator, or the window function of both comparator outputs. The voltage monitor’s ‘A’ output
indicates whether the input signal is between or outside the two comparator thresholds. Important: This windowing
function is only valid in cases where the threshold of the ‘A’ comparator is set to a value higher than that of the ‘B’
comparator. Table 1-4 shows the operation of window function logic.
Table 1-4. Voltage Monitor Windowing Logic
Note that when the ‘A’ output of the voltage monitor circuit is set to windowing mode, the ‘B’ output continues to
monitor the output of the ‘B’ comparator. This can be useful in that the ‘B’ output can be used to augment the win-
dowing function by determining if the input is above or below the windowing range.
The third section in the ispPAC-POWR1220AT8’s input voltage monitor is a digital filter. When enabled, the compar-
ator output will be delayed by a filter time constant of 64 µS, and is especially useful for reducing the possibility of
false triggering from noise that may be present on the voltages being monitored. When the filter is disabled, the
comparator output will be delayed by 16µS. In both cases, enabled or disabled, the filters also provide synchroniza-
tion of the input signals to the PLD clock. This synchronous sampling feature effectively eliminates the possibility of
race conditions from occurring in any subsequent logic that is implemented in the ispPAC-POWR1220AT8’s inter-
nal PLD logic.
The comparator status can be read from the I
SMBUS Interface section of this data sheet.
V
Trip-point B < V
Trip-point B < Trip-point A < V
IN
< Trip-point B < Trip-point A
Input Voltage
IN
< Trip-point A
IN
Low Limit
Comp A
0.664
1.119
1.326
1.583
1.884
2.236
3.156
4.045
4.815
0.79
0.94
2.65
Trip-point Range (V)
0
0
1
75 mV
2
C interface. For details on the I
High Limit
0.941
1.333
1.885
2.244
2.665
3.156
3.758
4.818
5.734
1-19
0.79
1.12
1.58
Comp B
0
1
1
Hysteresis (mV)
0 (Disabled)
ispPAC-POWR1220AT8 Data Sheet
(B and Not A)
10
12
14
17
20
24
28
34
40
51
61
8
Window
0
1
0
2
C interface, please refer to the I
Outside window, low
Inside window
Outside window, high
Comment
2
C/