isppac-powr1220at8 Lattice Semiconductor Corp., isppac-powr1220at8 Datasheet - Page 33

• Manufacturer Part Number: isppac-powr1220at8
• Description: In-system Programmable Power Supply Monitoring, Sequencing And Margining Controller
• Manufacturer: Lattice Semiconductor Corp.

Table 1-9. I
Lattice Semiconductor
Figure 1-23. I
The ispPAC-POWR1220AT8 provides 26 registers that can be accessed through its I
provide the user with the ability to monitor and control the device’s inputs and outputs, and transfer data to and
from the device. Table provides a summary of these registers.
Register Address
0x0A
0x0B
0x0C
0x0D
0x0E
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
STEP 1: WRITE REGISTER ADDRESS FOR READ OPERATION
STEP 2: READ DATA FROM THAT REGISTER
SDA
SDA
2
SCL
SCL
C Control Registers
2
C Read Operation
START
START
Register Name
adc_value_high
output_status0
output_status1
output_status2
adc_value_low
vmon_status0
vmon_status1
vmon_status2
input_status
input_value
UES_byte0
UES_byte1
UES_byte2
UES_byte3
gp_output1
gp_output2
gp_output3
A6
A6
trim1_trim
trim2_trim
trim3_trim
trim4_trim
trim5_trim
trim6_trim
adc_mux
1
1
reset
A5
A5
2
2
A4
A4
DEVICE ADDRESS (7 BITS)
DEVICE ADDRESS (7 BITS)
3
3
A3
A3
4
4
Read/Write
A2
A2
5
5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
A1
A1
W
R
R
R
R
R
R
R
R
R
R
R
R
R
6
6
A0
A0
7
7
R/W
R/W
VMON input status Vmon[4:1]
VMON input status Vmon[8:5]
VMON input status Vmon[12:9]
Output status OUT[8:5], HVOUT[4:1]
Output status OUT[16:9]
Output status OUT[20:17]
Input status IN[6:1]
ADC D[3:0] and status
ADC D[11:4]
ADC Attenuator and MUX[3:0]
UES[7:0]
UES[15:8]
UES[23:16]
UES[31:24]
GPOUT[8:1]
GPOUT[16:9]
GPOUT[20:17]
PLD Input Register [6:2]
Resets device on write
Trim DAC 1 [7:0]
Trim DAC 2 [7:0]
Trim DAC 3 [7:0]
Trim DAC 4 [7:0]
Trim DAC 5 [7:0]
Trim DAC 6 [7:0]
8
8
1-33
ACK
ACK
9
9
R7
D7
1
1
Description
R6
D6
2
2
ispPAC-POWR1220AT8 Data Sheet
REGISTER ADDRESS (8 BITS)
R5
D5
3
3
READ DATA (8 BITS)
R4
D4
4
4
R3
D3
5
5
R2
D2
6
6
Note: Shaded Bits Asserted by Slave
2
R1
D1
C interface. These registers
7
7
R0
D0
8
8
OPTIONAL
Value After POR
ACK
ACK
9
9
X X X X – – – –
– – – – X X X 1
X X X 1 1 1 1 1
X X X X 0 0 0 0
X X 0 0 0 0 0 X
X X – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
0 0 0 1 0 0 0 0
0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0
STOP
STOP
N/A
1, 2