isppac-powr1220at8 Lattice Semiconductor Corp., isppac-powr1220at8 Datasheet - Page 41

• Manufacturer Part Number: isppac-powr1220at8
• Description: In-system Programmable Power Supply Monitoring, Sequencing And Margining Controller
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
ispPAC-POWR1220AT8 Data Sheet
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Designs using the SMBAlert feature are required to set the device’s I
C/SMBus address to the lowest of all the
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addresses on that I
C/SMBus.
Software-Based Design Environment
Designers can configure the ispPAC-POWR1220AT8 using PAC-Designer, an easy to use, Microsoft Windows
compatible program. Circuit designs are entered graphically and then verified, all within the PAC-Designer environ-
ment. Full device programming is supported using PC parallel port I/O operations and a download cable connected
to the serial programming interface pins of the ispPAC-POWR1220AT8. A library of configurations is included with
basic solutions and examples of advanced circuit techniques are available on the Lattice web site for downloading.
In addition, comprehensive on-line and printed documentation is provided that covers all aspects of PAC-Designer
operation. The PAC-Designer schematic window, shown in Figure 1-33, provides access to all configurable ispPAC-
POWR1220AT8 elements via its graphical user interface. All analog input and output pins are represented. Static
or non-configurable pins such as power, ground, and the serial digital interface are omitted for clarity. Any element
in the schematic window can be accessed via mouse operations as well as menu commands. When completed,
configurations can be saved, simulated, and downloaded to devices.
Figure 1-33. PAC-Designer ispPAC-POWR1220AT8 Design Entry Screen
In-System Programming
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The ispPAC-POWR1220AT8 is an in-system programmable device. This is accomplished by integrating all E
con-
figuration memory and control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant
serial JTAG interface at normal logic levels. Once a device is programmed, all configuration information is stored
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on-chip, in non-volatile E
CMOS memory cells. The specifics of the IEEE 1149.1 serial interface and all ispPAC-
POWR1220AT8 instructions are described in the JTAG interface section of this data sheet.
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