isppac-powr1220at8 Lattice Semiconductor Corp., isppac-powr1220at8 Datasheet - Page 44

• Manufacturer Part Number: isppac-powr1220at8
• Description: In-system Programmable Power Supply Monitoring, Sequencing And Margining Controller
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
User Electronic Signature
A user electronic signature (UES) feature is included in the E
consists of 32 bits that can be configured by the user to store unique data such as ID codes, revision numbers or
inventory control data. The specifics of this feature are discussed in the IEEE 1149.1 serial interface section of this
data sheet.
Electronic Security
An electronic security “fuse” (ESF) bit is provided in every ispPAC-POWR1220AT8 device to prevent unauthorized
readout of the E
tional user bits in the device. This cell can only be erased by reprogramming the device, so the original configura-
tion cannot be examined once programmed. Usage of this feature is optional. The specifics of this feature are
discussed in the IEEE 1149.1 serial interface section of this data sheet.
Production Programming Support
Once a final configuration is determined, an ASCII format JEDEC file can be created using the PAC-Designer soft-
ware. Devices can then be ordered through the usual supply channels with the user’s specific configuration already
preloaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production
programming equipment, giving customers a wide degree of freedom and flexibility in production planning.
Evaluation Fixture
Included in the basic ispPAC-POWR1220AT8 Design Kit is an engineering prototype board that can be connected
to the parallel port of a PC using a Lattice download cable. It demonstrates proper layout techniques for the isp-
PAC-POWR1220AT8 and can be used in real time to check circuit operation as part of the design process. Input
and output connections are provided to aid in the evaluation of the ispPAC-POWR1220AT8 for a given application.
(Figure 1-36).
Figure 1-36. Download from a PC
IEEE Standard 1149.1 Interface (JTAG)
Serial Port Programming Interface Communication with the ispPAC-POWR1220AT8 is facilitated via an IEEE
1149.1 test access port (TAP). It is used by the ispPAC-POWR1220AT8 as a serial programming interface. A brief
description of the ispPAC-POWR1220AT8 JTAG interface follows. For complete details of the reference specifica-
tion, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1-1990
(which now includes IEEE Std 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the isp-
PAC-POWR1220AT8. The TAP controller is a state machine driven with mode and clock inputs. Given in the correct
sequence, instructions are shifted into an instruction register, which then determines subsequent data input, data
output, and related operations. Device programming is performed by addressing the configuration register, shifting
2
CMOS configuration bit patterns. Once programmed, this cell prevents further access to the func-
PAC-Designer
Software
1-44
ispDOWNLOAD
Cable (6')
2
CMOS memory of the ispPAC-POWR1220AT8. This
ispPAC-POWR1220AT8 Data Sheet
4
ispPAC-POWR
Circuitry
System
1220AT8
Other
Device