isppac-powr1220at8 Lattice Semiconductor Corp., isppac-powr1220at8 Datasheet - Page 24

• Manufacturer Part Number: isppac-powr1220at8
• Description: In-system Programmable Power Supply Monitoring, Sequencing And Margining Controller
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 1-14. Basic Function Diagram for an Output in High Voltage MOSFET Gate Driver Mode
Figure 1-14 shows the HVOUT circuitry when programmed as a FET driver. In this mode the output either sources
current from a charge pump or sinks current. The maximum voltage that the output level at the pin will rise to is also
programmable between 6V and 10V. The maximum voltage levels that are required depend on the gate-to-source
threshold of the FET being driven and the power supply voltage being switched. The maximum voltage level needs
to be sufficient to bias the gate-to-source threshold on and also accommodate the load voltage at the FET’s
source, since the source pin of the FET to provide a wide range of ramp rates is tied to the supply of the target
board. When the HVOUT pin is sourcing current, charging a FET gate, the source current is programmable
between 12.5µA and 100µA. When the driver is turned to the off state, the driver will sink current to ground, and
this sink current is also programmable between 3000µA and 100µA to control the turn-off rate.
Programmable Output Voltage Levels for HVOUT1- HVOUT4
There are three selectable steps for the output voltage of the FET drivers when in FET driver mode. The voltage
that the pin is capable of driving to can be programmed from 6V to 10V in 2V steps.
Controlling Power Supply Output Voltage by Margin/ Trim Block
One of the key features of the ispPAC-POWR1220AT8 is its ability to make adjustments to the power supplies that
it may also be monitoring and/or sequencing. This is accomplished through the Trim and Margin Block of the
device. The Trim and Margin Block can adjust voltages of up to eight different power supplies through TrimCells as
shown in Figure 1-15. The DC-DC blocks in the figure represent virtually any type of DC power supply that has a
trim or voltage adjustment input. This can be an off-the-shelf unit or custom circuit designed around a switching
regulator IC.
The interface between the ispPAC-POWR1220AT8 and the DC power supply is represented by a single resistor
(R1 to R8) to simplify the diagram. Each of these resistors represents a resistor network.
Other control signals driving the Margin/Trim Block are:
Next to each DC-DC converter, four voltages are shown. These voltages correspond to the operating voltage profile
of the Margin/Trim Block.
• VPS [1:0] – Control signals from device pins common to all eight TrimCells, which are used to select the
• PLD_VPS[1:0] – Voltage profile selection signals generated by the PLD. These signals can be used instead
• ADC input – Used to determine the trimmed DC-DC converter voltage.
• PLD_CLT_EN – Only from PLD, used to enable closed loop trimming of all TrimCells together.
active voltage profile for all TrimCells together.
of the VPS signals from the pins.
Digital Control
from PLD
Charge Pump
(6 to 10V)
from I
Digital Control
2
+
C Register
-
(100 to 500 µA)
+Fast Turn-off
(3000µA)
I
SINK
1-24
(12.5 to 100 µA)
I
SOURCE
ispPAC-POWR1220AT8 Data Sheet
HVOUTx
Pin
Supply
Input
Load