isppac-powr1220at8 Lattice Semiconductor Corp., isppac-powr1220at8 Datasheet - Page 54

• Manufacturer Part Number: isppac-powr1220at8
• Description: In-system Programmable Power Supply Monitoring, Sequencing And Margining Controller
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Revision History
October 2005
October 2006
August 2007
March 2006
June 2008
May 2006
Date
Version
01.4
01.5
1.0
1.1
1.2
1.3
Initial release.
Pin Descriptions table, note 4: Clarification for un-used VMON pins to be tied to
GNDD.
Correction for I
Updated HVOUT Isource range:12.5µA to 100µA.
ADC Characteristics table, ADC Conversion Time: added entry for Tconvert = 200 µs.
Added footnotes for I
Figure 13, Isource 12.5µA to 100µA.
Clarified operation of ADC conversions.
TAP instructions, added JTAG SAMPLE/PRELOAD instruction and notes for all JTAG
instructions
Data sheet status changed to “final”.
Analog Specifications table, lowered Max. Icc to 40 mA.
Voltage Monitors table, tightened Input Resistor Variation to 15%.
Margin Trim DAC Output Characteristics table, increased Max. DAC output current to
+/- 200 µA.
AC/Transient Characteristics table, tightened Internal Oscillator frequency variation
down to 5%.
Digital Specifications table, included V
Changes to HVOUT pin specifications.
Added timing diagram and timing parameters to "Power-On Reset" specifications.
Modified PLD Architecture figure to show input registers.
Updated I
V
CCPROG
2
pin usage clarification added.
C Control Registers table.
2
C/ADC calculation.
1-54
2
C frequency.
Change Summary
ispPAC-POWR1220AT8 Data Sheet
IL
and V
IH
specifications for I
2
C interface.