isppac-powr1220at8 Lattice Semiconductor Corp., isppac-powr1220at8 Datasheet - Page 50

• Manufacturer Part Number: isppac-powr1220at8
• Description: In-system Programmable Power Supply Monitoring, Sequencing And Margining Controller
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
ispPAC-POWR1220AT8 Data Sheet
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UES_PROGRAM – This instruction will program the content of the UES Register into the UES E
CMOS memory.
The device must already be in programming mode (PROGRAM_ENABLE instruction). This instruction also forces
the outputs into the OUTPUTS_HIGHZ.
ERASE_DONE_BIT – This instruction clears the 'Done' bit, which prevents the ispPAC-POWR1220AT8 sequence
from starting.
PROGRAM_DONE_BIT – This instruction sets the 'Done' bit, which enables the ispPAC-POWR1220AT8
sequence to start.
RESET – This instruction resets the PLD sequence and output macrocells.
IN1_RESET_JTAG_BIT – This instruction clears the JTAG Register logic input 'IN1.' The PLD input has to be con-
figured to take input from the JTAG Register in order for this command to have effect on the sequence.
IN1_SET_JTAG_BIT – This instruction sets the JTAG Register logic input 'IN1.' The PLD input has to be configured
to take input from the JTAG Register in order for this command to have effect on the sequence.
PLD_VERIFY_INCR – This instruction reads out the PLD data register for the current address and increments the
address register for the next read.
Notes:
In all of the descriptions above, OUTPUTS_HIGHZ refers both to the instruction and the state of the digital output
pins, in which the open-drains are tri-stated and the FET drivers are pulled low.
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Before any of the above programming instructions are executed, the respective E
CMOS bits need to be erased
using the corresponding erase instruction.
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