hyb514100bj-60 Infineon Technologies Corporation, hyb514100bj-60 Datasheet - Page 20

• Manufacturer Part Number: hyb514100bj-60
• Manufacturer: Infineon Technologies Corporation

Test Mode Entry
Test Mode
The HYB 514100BJ is organized 4 194 304 words by 1-bit but can internally be configured as
524 288 words by 8-bits. A WE, CAS-before-RAS cycle puts the device into Test Mode.
In Test Mode, data is written into 8 sectors in parallel and retrieved the same way. If, upon reading,
all bits are equal, the data output pin indicates a “1”. If any of the bits differ, the data output pin
indicates a “0”. In Test Mode the 4M DRAM can be tested as if it were a 512K DRAM. Test Mode
is exited by any refresh operation which is not a WE, CAS-before-RAS cycle. Addresses A10R,
A10C and A0C do not care during Test Mode.
Semiconductor Group
RAS
CAS
A0 A10
WE
DO
(Output) V
-
V
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
OH
OL
"H" or "L"
t
OFF
t
RPG
t
CP
t
RP
t
WTS
t
CSR
t
t
WTH
CHR
20
t
RAS
Hi
t
Z
RC
HYB 514100BJ-50/-60
t
RPC
t
RP
t
ASR
4M
t
CRP
Address
Row
1998-10-01
1 DRAM
SPT03024