hyb514100bj-60 Infineon Technologies Corporation, hyb514100bj-60 Datasheet - Page 8

• Manufacturer Part Number: hyb514100bj-60
• Manufacturer: Infineon Technologies Corporation

Notes
1. All voltages are referenced to
2.
3.
4. Address can be changed once or less while RAS =
5. An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least
6. AC measurements assume
7.
8. Measured with a load equivalent to 2 TTL loads and 100 pF.
9. Operation within the
10.Operation within the
11.Either
12.
13.
14.These parameters are referenced to the CAS leading edge in early write cycles and to the WE
Semiconductor Group
I
I
or less during a fast page mode cycle (
one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using
internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS
cycles are required.
V
are also measured between
a reference point only: If
controlled by
a reference point only: If
controlled by
referenced to output voltage levels.
data sheet as electrical characteristics only. If
and the data out pin will remain open-circuit (high impedance) through the entire cycle; if
t
write cycle and DO will contain data read from the selected cells. If neither of the above sets of
conditions is satisfied, the condition of the DO pin (at access time) is indeterminate.
leading edge in read-write cycles.
t
t
RWD
CC1
CC1
OFF (MAX.)
WCS
IH (MIN.)
,
and
,
>
I
t
CC3
RWD
t
t
RWD (MIN.)
RCH
and
I
,
CC4
,
defines the time at which the outputs achieve the open-circuit condition and are not
I
CC4
t
or
CWD
V
depend on output loading. Specified values are measured with the output open.
t
t
CAC
AA
t
IL (MAX.)
and
RRH
,
,
.
t
.
AWD
t
CWD
must be satisfied for a read cycle.
I
CC6
t
t
are reference levels for measuring timing of input signals. Transition times
and
RCD (MAX.)
RAD (MAX.)
>
depend on cycle rate.
t
CWD (MIN.)
t
t
t
RCD
CPWD
RAD
t
V
T
V
IH
= 5 ns.
is greater than the specified
is greater than the specified
limit ensures that
limit ensures that
are not restrictive operating parameters. They are included in the
SS
and
,
.
t
AWD
V
IL
t
.
PC
>
t
).
AWD(MIN.)
8
t
WCS
t
t
RAC (MAX.)
RAC (MAX.)
V
and
>
IL
. In the case of
t
WCS (MIN.)
t
CPWD
can be met.
can be met.
t
t
RCD (MAX.)
RAD (MAX.)
>
, the cycle is an early write cycle
t
CPWD (MIN.)
HYB 514100BJ-50/-60
I
CC4
limit, then access time is
limit, then access time is
t
t
RCD (MAX.)
RAD (MAX.)
it can be changed once
, the cycle is a read-
4M
is specified as
is specified as
1998-10-01
1 DRAM