hy5du561622efp Hynix Semiconductor, hy5du561622efp Datasheet - Page 11

• Manufacturer Part Number: hy5du561622efp
• Description: 256mb Ddr Sdram
• Manufacturer: Hynix Semiconductor

Rev. 1.1 / June 2006
POWER-UP SEQUENCE AND DEVICE INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those
specified may result in undefined operation. Power must first be applied to VDD, then to VDDQ, and finally to VREF
(and to the system VTT). VTT must be applied after VDDQ to avoid device latch-up, which may cause permanent dam-
age to the device. VREF can be applied anytime after VDDQ, but is expected to be nominally coincident with VTT.
Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input, but will detect an
LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to
guarantee that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal oper-
ation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR
SDRAM requires a 200us delay prior to applying an executable command.
Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be
brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDED
MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODE
REGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the operating
parameters. After the DLL reset, tXSRD(DLL locking time) should be satisfied for read command. After the Mode Reg-
ister set command, a PRECHARGE ALL command should be applied, placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command
for the Mode Register, with the reset DLL bit deactivated low (i.e. to program operating parameters without resetting
the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.
1.
2.
3.
4.
5.
6.
7.
8.
• VDD and VDDQ are driven from a single power converter output.
• VTT is limited to 1.44V (reflecting VDDQ(max)/2 + 50mV VREF variation + 40mV VTT variation.
• VREF tracks VDDQ/2.
• A minimum resistance of 42 Ohms (22 ohm series resistor + 22 ohm parallel resistor - 5% tolerance) limits the
• If the above criteria cannot be met by the system design, then the following sequencing and voltage relation-
Apply power - VDD, VDDQ, VTT, VREF in the following power up sequencing and attempt to maintain CKE at LVC-
MOS low state. (All the other input pins may be undefined.)
Start clock and maintain stable clock for a minimum of 200usec.
After stable power and clock, apply NOP condition and take CKE high.
Issue Extended Mode Register Set (EMRS) to enable DLL.
Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200
cycles(tXSRD) of clock are required for locking DLL)
Issue Precharge commands for all banks of the device.
Issue 2 or more Auto Refresh commands.
Issue a Mode Register Set command to initialize the mode register with bit A8 = Low
input current from the VTT supply into any pin.
ship must be adhered to during power up.
Voltage description
VDDQ
VREF
VTT
After or with VDDQ
After or with VDDQ
After or with VDD
Sequencing
Voltage relationship to avoid latch-up
< VDDQ + 0.3V
< VDDQ + 0.3V
< VDD + 0.3V
HY5DU561622E(L)FP
HY5DU56822E(L)FP
11