hy5du561622efp Hynix Semiconductor, hy5du561622efp Datasheet - Page 8

• Manufacturer Part Number: hy5du561622efp
• Description: 256mb Ddr Sdram
• Manufacturer: Hynix Semiconductor

Rev. 1.1 / June 2006
SIMPLIFIED COMMAND TRUTH TABLE
Note:
1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
*For more information about Truth Table, refer to “Device Operation” section in hynix website.
Extended Mode Register Set
Precharge Power
Write with Autoprecharge
Read with Autoprecharge
completely written.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Precharge command.
to activated bank until CK(n+BL/2+tRP).
to activated bank until CK(n+BL/2+1+tWR+tRP). Write Recovery Time (tWR) is needed to guarantee that the last data has been
precharged.
Precharge selected Bank
Self Refresh
Down Mode
Active Power
Down Mode
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
Precharge All Banks
Mode Register Set
Read Burst Stop
Device Deselect
No Operation
Auto Refresh
Bank Active
Command
Write
Read
1
1
1
1
1
1
1
1
1
1
Entry
Entry
Entry
1,2
Exit
Exit
Exit
1,5
1,3
1,4
1
1,2
CKEn-1
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
CKEn
H
H
H
H
X
X
X
X
X
X
X
X
L
L
L
/CS
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
/RAS
H
H
H
H
H
H
H
L
L
X
L
L
L
L
X
X
X
X
V
X
/CAS
H
H
H
H
H
H
H
L
L
X
L
L
L
L
X
X
X
X
V
/WE
H
H
H
H
H
H
H
H
L
L
X
L
L
L
X
X
X
X
V
HY5DU561622E(L)FP
HY5DU56822E(L)FP
ADDR
CA
CA
X
RA
OP code
OP code
A10/AP
X
X
X
X
X
X
H
H
H
L
L
L
BA
V
V
V
X
V
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