hy5du561622efp Hynix Semiconductor, hy5du561622efp Datasheet - Page 19

• Manufacturer Part Number: hy5du561622efp
• Description: 256mb Ddr Sdram
• Manufacturer: Hynix Semiconductor

Rev. 1.1 / June 2006
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7
IDD1: Operating current: One bank operation
1. Typical Case: VDD = 2.5V, T=25
2. Worst Case: VDD = 2.7V, T= 0
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are
4. Timing patterns
IDD7: Operating current: Four bank operation
1. Typical Case: VDD = 2.5V, T=25
2. Worst Case: VDD = 2.7V, T= 0
3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
4. Timing patterns
- DDR200(100Mhz, CL=2): tCK = 10ns, CL2, BL=2, tRCD = 2*tCK, tRC = 10*tCK, tRAS = 5*tCK
- DDR266B(133Mhz, CL=2.5): tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
- DDR266A (133Mhz, CL=2): tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
- DDR333(166Mhz, CL=2.5): tCK = 6ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 10*tCK, tRAS = 7*tCK
- DDR400(200Mhz, CL=3): tCK = 5ns, CL=3, BL=4, tRCD = 3*tCK, tRC = 11*tCK, tRAS = 8*tCK
changing. lout = 0mA
- DDR200(100Mhz, CL=2): tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with Autoprecharge
- DDR266B(133Mhz, CL=2.5): tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK Read with autoprecharge
- DDR266A (133Mhz, CL=2): tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
- DDR333(166Mhz, CL=2.5): tCK = 6ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
- DDR400(200Mhz, CL=3): tCK = 5ns, CL = 2, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
Read: A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
changing once per clock cycle. lout = 0mA
Read: A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
Read: A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
Read: A0 N N R0 N N N P0 N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
Read: A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
50% of data changing at every burst
Read: A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
Legend: A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Legend: A=Activate, R=Read, W=Write, P=Precharge, N=NOP
o
o
C
C
o
o
C for DDR200, 266, 333; VDD = 2.6V, T=25
C for DDR200, 266, 333; VDD = 2.6V, T=25
o
o
C for DDR400
C for DDR400
HY5DU561622E(L)FP
HY5DU56822E(L)FP
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