hy5du561622efp Hynix Semiconductor, hy5du561622efp Datasheet - Page 27

• Manufacturer Part Number: hy5du561622efp
• Description: 256mb Ddr Sdram
• Manufacturer: Hynix Semiconductor

Rev. 1.1 / June 2006
Note:
1. Pullup slew rate is characterized under the test conditions as shown in below Figure.
2. Pulldown slew rate is measured under the test conditions shown in below Figure.
3. Pullup slew rate is measured between (VDDQ/2 - 320 mV ± 250mV)
Example: For typical slew, DQ0 is switching
4. Evaluation conditions
5. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature
6. Verified under typical conditions for qualification purposes.
7. TSOP-II package devices only.
8. Only intended for operation up to 256 Mbps per pin.
9. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5 V/ns as shown in Table b.
10. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables c
11. Table c is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the
12. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal tran-
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output
Pulldown slew rate is measured between (VDDQ/2 + 320mV ± 250mV)
Typical: 25
Minimum: 70
Maximum: 0
{1/(Slew Rate1)} - {1/(slew Rate2)}
For example:
If Slew Rate 1 is 0.5 V/ns and Slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is -0.5 ns/V. Using the table given, this would
switching.
and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process
variation.
The Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), sim-
ilarly for rising transitions.
& d. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, fall rate. Input slew rate is based on
the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The
delta rise/fall rate is calculated as:
result in the need for an increase in tDS and tDH of 100ps.
lesser of the AC-AC slew rate and the DC-DC slew rate. The input slew rate is based on the lesser of the slew rates determined by
either VIH(ac) to VIL(AC) or VIH(DC) to VIL(DC), and similarly for rising transitions.
sitions through the DC region must be monotonic.
For minimum slew rate, all DQ bits are switching worst case pattern
For maximum slew rate, only one DQ is switching from either high to low, or low to high.
The remaining DQ bits remain the same as for previous state.
o
C (Ambient), VDDQ = nominal, typical process
o
(VOUT)
Output
(VOUT)
o
Output
C (Ambient), VDDQ = Maximum, fast-fast process
C (Ambient), VDDQ = minimum, slow-slow process
VSSQ
VDDQ
50
50
Ω
Ω
Test Point
Test Point
Figure: Pullup Slew rate
Figure: Pulldown Slew rate
HY5DU561622E(L)FP
HY5DU56822E(L)FP
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