hy5du561622efp Hynix Semiconductor, hy5du561622efp Datasheet - Page 25

• Manufacturer Part Number: hy5du561622efp
• Description: 256mb Ddr Sdram
• Manufacturer: Hynix Semiconductor

Rev. 1.1 / June 2006
20.tQH = tHP - tQHS, where:
21. tDQSQ:
22. tDAL = (tWR/tCK) + (tRP/tCK)
23. In all circumstances, tXSNR can be satisfied using
24. The only time that the clock frequency is allowed to change is during self-refresh mode.
25. If refresh timing or tDS/tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The
Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given
For each of the terms above, if not already an integer, round to the next highest integer.
Example: For DDR266B at CL=2.5 and tCK=7.5 ns
tDAL = ((15 ns / 7.5 ns) + (20 ns / 7.5 ns)) clocks
= ((2) + (3)) clocks
= 5 clocks
tXSNR = tRFCmin + 1*tCK
pulse duration distortion of on-chip clock circuits; and 2) The worst case push--out of DQS on one transition followed by the
worst case pull--in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects,
and p-channel to n-channel variation of the output drivers.
cycle.
READ can be executed.
HY5DU561622E(L)FP
HY5DU56822E(L)FP
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