hy5du561622efp Hynix Semiconductor, hy5du561622efp Datasheet - Page 13

• Manufacturer Part Number: hy5du561622efp
• Description: 256mb Ddr Sdram
• Manufacturer: Hynix Semiconductor

Rev. 1.1 / June 2006
MODE REGISTER SET (MRS)
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,
burst type, test mode, DLL reset. The mode register is programed via MRS command. This command is issued by the
low signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and
CKE must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to
write the data in mode register. During the MRS cycle, any command cannot be issued. Once mode register field is
determined, the information will be held until reset by another MRS command.
BA0
A12~A9
BA1
0
1
0
0
0
0
-
MRS Type
BA0
A8
0
EMRS
0
1
0
MRS
-
A7
0
0
1
-
A12
A6~A0
Valid
Valid
VS
-
A11
Operating Mode
A10
Normal Operation/ Reset DLL
Vendor specific Test Mode
A6
All other states reserved
0
0
0
0
1
1
1
1
Normal Operation
Operating Mode
A5
A9
0
0
1
1
0
0
1
1
A4
0
1
0
1
0
1
0
1
A8
CAS Latency
Reserved
Reserved
Reserved
Reserved
1.5
2.5
A7
2
3
A6
CAS Latency
A5
A2
0
0
0
0
1
1
1
1
A4
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
A3
HY5DU561622E(L)FP
A3
BT
0
1
HY5DU56822E(L)FP
Sequential
Reserved
Reserved
Reserved
Reserved
Reserved
Burst Type
Sequential
Interleave
A2
2
4
8
Burst Length
Burst Length
A1
Interleave
Reserved
Reserved
Reserved
Reserved
Reserved
2
4
8
A0
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