hy5du561622efp Hynix Semiconductor, hy5du561622efp Datasheet - Page 3

• Manufacturer Part Number: hy5du561622efp
• Description: 256mb Ddr Sdram
• Manufacturer: Hynix Semiconductor

Rev. 1.1 / June 2006
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ORDERING INFORMATION
* x means speed grade
* ROHS (Restriction Of Hazardous Substances)
DESCRIPTION
The HY5DU56822E(L)FP, and HY5DU561622E(L)FP are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous
DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
This Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
HY5DU561622E(L)F-x*
HY5DU56822E(L)F-x*
V
V
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
x16 device has two bytewide data strobes (UDQS,
LDQS) per each x8 I/O
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
On chip DLL align DQ and DQS transition with CK
transition
DM mask write data-in at the both rising and falling
edges of the data strobe
DD
DD
Part No.
, V
, V
DDQ
DDQ
= 2.5V
= 2.6V +0.1V / -0.2V for DDR400
±
Configuration
0.2V for DDR200, 266, 333
16M x 16
32M x 8
60 Ball FBGA
(Lead free)
Package
OPERATING FREQUENCY
Grade
-D43
- K
- H
- L
- J
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All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
Programmable CAS latency 2/2.5 (DDR200, 266,
333) and 3 (DDR400) supported
Programmable burst length 2/4/8 with both sequen-
tial and interleave mode
Internal four bank operations with single pulsed
/RAS
Auto refresh and self refresh supported
tRAS lock out function supported
8192 refresh cycles / 64ms
60 Ball FBGA Package Type
Full and Half strength driver option controlled by
EMRS
Lead free (*ROHS Compliant)
133MHz@CL2
133MHz@CL2
100MHz@CL2
200MHz@CL3
100MHz@CL2
Clock Rate
166MHz@CL2.5
133MHz@CL2.5
133MHz@CL2.5
HY5DU561622E(L)FP
HY5DU56822E(L)FP
DDR400B (3-3-3)
DDR333 (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR200 (2-2-2)
(CL-tRCD-tRP)
Remark
3