lp62s1024ax-70llt AMIC Technology Corporation, lp62s1024ax-70llt Datasheet
lp62s1024ax-70llt
Available stocks
Related parts for lp62s1024ax-70llt
lp62s1024ax-70llt Summary of contents
Page 1
Features n Power supply range: 2.7V to 3.6V n Access times: 55/70 ns (max.) n Current: Very low power version: Operating:(70NS)30mA(max.) Standby:5uA (max.) n Full static operation, no clock or refreshing required General Description The LP62S1024A low operating ...
Page 2
Block Diagram A0 A14 A15 A16 I/O 1 I/O 8 CE2 CE1 CONTROL CIRCUIT OE WE Pin Descriptions - SOP Pin No. Symbol Connection 2 - 12, 23 A16 Address Inputs 25 - 28, 31 ...
Page 3
Pin Description - CSP Symbol Description A0 - A16 Address Inputs Write Enable WE Output Enable OE Chip Enable CE1 CE2 Chip Enable Recommended DC Operating Conditions ( Symbol Parameter VCC Supply Voltage ...
Page 4
Absolute Maximum Ratings* VCC to GND .............................................. -0.5V to +4.6V IN, IN/OUT Volt to GND .....................-0.5V to VCC +0.5V Operating Temperature, Topr ................... - +85 C Storage Temperature, Tstg..................... - +125 C Temperature Under Bias, Tbias................ ...
Page 5
DC Electrical Characteristics (continued) Symbol Parameter Standby Power SB1 Supply Current I SB2 Output Low V OL Voltage Output High V OH Voltage Truth Table Mode CE1 H Standby X Output Disable L Read L Write L ...
Page 6
AC Characteristics ( +85 C, VCC = 2.7V to 3.6V) A Symbol Parameter Read Cycle t Read Cycle Time RC t Address Access Time AA t ACE1 Chip Enable Access Time t ACE2 t Output Enable ...
Page 7
Timing Waveforms ( Read Cycle 1 Address D OUT ( Read Cycle 2 CE1 t D OUT ( Read Cycle 3 CE2 t D OUT (August, 2001, Version 1. ...
Page 8
Timing Waveforms (continued) (1) Read Cycle 4 Address OE CE1 CE2 D OUT Notes high for Read Cycle. 2. Device is continuously enabled CE1 = V 3. Address valid prior to or coincident with CE1 transition low. ...
Page 9
Timing Waveforms (continued) (6) Write Cycle 1 (Write Enable Controlled) Address CE1 CE2 OUT (August, 2001, Version 1. (4) ( ...
Page 10
Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) Address CE1 CE2 OUT Notes measured from the address valid to the beginning of Write Write occurs during the overlap (t ...
Page 11
AC Test Conditions Input Pulse Levels Input Rise and Fall Time Input and Output Timing Reference Levels Output Load Including scope and jig. Figure 1. Output Load Data Retention Characteristics Symbol Parameter V DR1 VCC for Data ...
Page 12
Low VCC Data Retention Waveform (1) ( CE1 Controlled) VCC 3.0V t CDR V CE1 IH Low VCC Data Retention Waveform (2) (CE2 Controlled) VCC 3.0V t CDR CE2 V IL (August, 2001, Version 1.0) DATA RETENTION MODE V 2V ...
Page 13
... Ordering Information Part No. Access Time (ns) LP62S1024AM-55LLT LP62S1024AV-55LLT LP62S1024AX-55LLT LP62S1024AU-55LLT LP62S1024AM-70LLT LP62S1024AV-70LLT LP62S1024AX-70LLT LP62S1024AU-70LLT (August, 2001, Version 1.0) LP62S1024A-T Series Operating Current Standby Current Max. (mA) Max Package 32L SOP 32L TSOP 32L TSSOP 36L CSP ...
Page 14
Package Information SOP (W.B.) 32L Outline Dimensions Seating Plane Symbol e Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e reference only. ...
Page 15
Package Information TSOP 32L TYPE 20mm) Outline Dimensions y Symbol Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e reference only. 4. Dimension S ...
Page 16
Package Information TSSOP 32L TYPE 13.4mm) Outline Dimensions 0.10MM SEATING PLANE Symbol Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e reference only. 4. ...
Page 17
Package Information 36LD CSP ( mm) Outline Dimensions Note: 1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY). ...