ql6325-4pt280c QuickLogic Corp, ql6325-4pt280c Datasheet
ql6325-4pt280c
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ql6325-4pt280c Summary of contents
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... Applications • Signal processing operators • Signal processing functions • Networking/communications for VoIP • Speech/voice processing • Channel coding © 2007 QuickLogic Corporation Programmable I/O • High performance: <3.2 ns Tco • Programmable slew rate control • Programmable I/O standards: LVTTL, LVCMOS, PCI, GTL+, SSTL2, ...
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... Table 2: Max I/O per Device /Package Combination 208 PQFP 280 FPBGA 99 163 99 163 - 163 - 163 . Eclipse is available in commercial, industrial, and military CCIO 2. This architectural feature addresses current register- Figure QL6325 QL6500 320,640 488,064 48x32 64x48 1,536 3,072 4,002 7,185 310 347 24 32 55,300 ...
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... It has 6 outputs; 4 combinatorial and 2 registered. The high logic capacity and fan-in of the logic cell accommodate many user functions with a single level of logic delay while other architectures require two or more levels of delay. © 2007 QuickLogic Corporation Figure 2: Eclipse Logic Cell QS ...
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... Figure 3: 2,304-bit Eclipse RAM Module MODE[1:0] ASYNCRD WA[9:0] RA[9:0] WD[17:0] RD[17:0] WE WCLK Figure 4. Figure 4: Cascaded RAM Modules WDATA RAM Module (2,304 bits) WADDR RAM Module (2,304 bits) WDATA RE RCLK RDATA RADDR RDATA © 2007 QuickLogic Corporation ...
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... QuickLogic ESP PLL. Figure 5 Frequency Divide FIN FOUT © 2007 QuickLogic Corporation 4. The QuickLogic built-in PLLs support a wider range of Table Figure 5: PLL Block PLL Bypass + vco Filter - Frequency Multiply ...
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... MHz–300 MHz signal and the in a Output Frequency Range 66 MHz–150 MHz 25 MHz–133 MHz 100 MHz–250 MHz 32 MHz–100 MHz 50 MHz–125 MHz 25 MHz–50 MHz 64 MHz–160 MHz 25 MHz–75 MHz © 2007 QuickLogic Corporation ...
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... Because PLLCLK_IN and PLLRST signals have INPAD, and PLLPAD_OUT has OUTPAD, you do not have to add additional pads to your design. NOTE: For PLL AC specifications, contact the factory. © 2007 QuickLogic Corporation Table 5: PLL Signals Description If PLLRST is asserted, then CLKNET_OUT and PLLPAD_OUT are reset to 0. ...
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... For voltage referenced CCIO pins must be tied to a 3.3 V supply to provide 3.3 V compliance. Eclipse can Table 6: I/O Standards and Applications INREF Reference Output Voltage Voltage n/a 3.3 n/a 2.5 n/a 3.3 1.0 n/a 1.5 3.3 1.25 2.5 Table 6). Application General Purpose General Purpose PCI Bus Applications Backplane SDRAM SDRAM © 2007 QuickLogic Corporation ...
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... For combinatorial control operation data is routed from the logic array through a multiplexer to the three-state control. The IOCTRL pins can directly drive the OE and CLK signals for all I/O cells within the same bank. © 2007 QuickLogic Corporation Figure 6: Eclipse I/O Cell INPUT ...
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... Figure 7 Figure 7: Multiple I/O Banks VCCIO 1 INREF 0 Embedded RAM Blocks Fabric Embedded RAM Blocks INREF 5 VCCIO 4 illustrates the I/O bank and INREF supply CCIO and CCIO INREF 1 PLL VCCIO 2 INREF 2 VCCIO 3 PLL INREF 3 INREF 4 © 2007 QuickLogic Corporation ...
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... Programmable weak-pull down resistor is available on each I/O. The I/O Weak Pull-Down eliminates the need for external pull down resistor for used I/O. The spec for pull-down current is maximum of 150 µA under worst case condition. © 2007 QuickLogic Corporation Figure 8: Programmable I/O Weak Pull-Down I/O Output Logic Eclipse Family Data Sheet Rev ...
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... RAM blocks in the device. Five global clocks have access to a Quad Net (local clock network) connection with a programmable connection to the register inputs. Global clock pins are 2.5 V, LVCMOS2, compliant. • • 12 www.quicklogic.com • • • • Figure 9: Global Clock Methodology CLK Pin Quad Net Global Clock Net © 2007 QuickLogic Corporation ...
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... Input Dedicated Clock There is one dedicated clock each device of the Eclipse Family (QL6250, QL6325, QL6500, and QL6600). This clock connects to the clock input of the Logic Cell and I/O registers, and RAM blocks through a hardwired connection and is multiplexed with the programmable clock input. The dedicated clock provides a fast global network with low skew ...
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... Logic ‘1’, you must assert the “Set” signal after the Global POR signal has been deasserted. • • 14 www.quicklogic.com • • • • Figure 12: Power-On Reset VCC Power-on Reset XXXXXXX 0 Q and CC © 2007 QuickLogic Corporation ...
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... TDI and TDO pins. For this test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the functional data entering and leaving the device. © 2007 QuickLogic Corporation Figure 13: JTAG Block Diagram Instruction Decode & ...
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... Power-Up Loading is not enabled and the JTAG pins function as they normally would. The option to program this bit is selectable via QuickWorks in the Tools/Options/Device Programming window in SpDE. For more information on Power-Up Loading refer to QuickLogic Application Note 55 at http://www.quicklogic.com/images/appnote55.pdf. • • 16 www.quicklogic.com • • • • © 2007 QuickLogic Corporation ...
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... V . Therefore, these output pins can only drive CCIO LVCMOS2 compliant only (2.5 V). © 2007 QuickLogic Corporation Table 7: JTAG Pin Descriptions Description Hold HIGH during normal operation. Connects to serial PROM data in for RAM initialization. Connect to VCC if unused Hold LOW during normal operation. Connects to serial PROM reset for RAM initialization ...
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... Table 9: Operating Range Military Min. Max. 2.3 2.7 2.3 3.6 -55 - 125 0.42 2.3 0.42 1.92 0.42 1.35 0.42 1.27 12. Parameter Value ±20 mA ±2000 V -65° 150° C -55° 125° C rail, not the V CC Industrial Commercial Min. Max. Min. Max. 2.3 2.7 2.3 2.7 2.3 3.6 2.3 3.6 - 0.43 2.16 0.47 2.11 0.43 1.80 0.46 1.76 0.43 1.26 0.46 1.23 0.43 1.19 0.46 1.16 © 2007 QuickLogic Corporation . CCIO Unit V V °C °C n/a n/a n/a n/a ...
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... All dedicated inputs including the CLK, DEDCLK, PLLIN, PLLRST, and IOCTRL pins, are clamped to the V rail, not the V . Therefore, these pins can only be driven CCIO are LVCMOS2 compliant only (2.5 V). © 2007 QuickLogic Corporation Table 10: DC Characteristics Conditions CCIO ...
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... VccI/O = 2.3V -40 VccI/O = 2.5V -60 VccI/O = 2.7V VccI/0 = 3.0V -80 VccI/O = 3.3V -100 VccI/O = 3.6V -120 • • 20 www.quicklogic.com • • • • Figure 14: IOL vs. VOL IOL vs VOL 0.60 0.80 1.00 1.20 1.40 1.60 1.80 Supply voltage (V) Figure 15: IOH vs. VOH IOH vs VOH Supply voltage (V) Vccio = 3.6V Vccio = 3.3V Vccio = 3.0V Vccio = 2.7V Vccio = 2.5V Vccio = 2.3V 2.00 2.20 2.40 2.60 2.80 3.00 © 2007 QuickLogic Corporation ...
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... Set Width: time that the SET signal remains high/low SW t Reset Width: time that the RESET signal remains high/low RW © 2007 QuickLogic Corporation = 2 25° 1.00 21. Logic Cell diagrams and waveforms are Table 13 Table 21. Figure 16: Eclipse Logic Cell ...
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... Figure 17: Logic Cell Flip Flop SET D CLK RESET Figure 18: Logic Cell Flip Flop Timings - First Waveform t (min) CWHI t RESET t RW Figure 19: Logic Cell Flip Flop Timings - Second Waveform (min) CWLO t SET t SW © 2007 QuickLogic Corporation ...
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... Global clock pin delay to quad net PGCK t Global clock buffer delay (quad net to flip flop) BGCK Programmable Clock External Clock © 2007 QuickLogic Corporation Figure 20: Eclipse Global Clock Structure Table 14: Eclipse Global Clock Tree Delays Parameter Figure 21: Global Clock Structure Schematic Global Clock Buffer Clock ...
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... WRITE DATA must be stable after the active time the WRITE ENABLE must be stable before the time the WRITE ENABLE must be stable after the time between the active WRITE CLOCK edge and the RE [9:0] RA [17:0] RD Min. 0.675 0.654 0.276 © 2007 QuickLogic Corporation Value Max 2.796 ns ...
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... READ CLOCK edge and the time when the t RCRD data is available at RD RAM Cell Asynchronous Read Timing RA to RD: time between when the READ ADDRESS is input and when the DATA r PDRD is output © 2007 QuickLogic Corporation Figure 23: RAM Cell Synchronous Write Timing t t SWA HWA t t SWD HWD ...
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... Figure 24: RAM Cell Synchronous and Asynchronous Read Timing RCLK • • 26 www.quicklogic.com • • • • t SRA t SRE old data r PDRD Figure 25: Eclipse Cell I/O INPUT REGISTER R Q OUTPUT D REGISTER OUTPUT ENABLE D REGISTER R t HRA t HRE new data t RCRD + - PAD © 2007 QuickLogic Corporation ...
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... IRST when the output is consequently “reset” (low) Input register clock enable setup time: t IESU active clock edge Input register clock enable hold time: t IEH active clock edge © 2007 QuickLogic Corporation Figure 26: Eclipse Input Register Cell t ICLK INI Q E ...
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... Low Voltage CMOS for 2.5 V and lower applications Gunning Transceiver Logic Stub Series Terminated Logic for 3.3 V Stub Series Terminated Logic for 2.5 V Figure 27: Eclipse Input Register Cell Timing t t ISU IHL t ICO t t IESU IEH Value Min. ISU - IRST © 2007 QuickLogic Corporation Max. ...
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... Output Delay high to tri-State PHZ t Output Delay low to tri-State PLZ t Clock to out delay (does not include clock tree delays) COP © 2007 QuickLogic Corporation Figure 28: Eclipse Output Register Cell Table 19: Eclipse Output Register Cell Parameter Eclipse Family Data Sheet Rev. F PAD Value Min. ...
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... Figure 29: Eclipse Output Register Cell Timing H t OUTLH H t PZH PLZ Table 20: Output Slew Rates @ V Fast Slew Rising Edge 2.8 V/ns 2.86 V/ns Table 21: Output Slew Rates @ V Fast Slew 1.7 V/ns 1.9 V/ns t OUTHL L t PZL Z t PHZ 3.3 V CCIO Slow Slew 1.0 V/ns 1.0 V/ns = 2.5 V CCIO Slow Slew 0.6 V/ns 0.6 V/ns © 2007 QuickLogic Corporation ...
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... Pin Package Count Type 516 PBGA 484 PBGA 280 LFBGA 208 PQFP © 2007 QuickLogic Corporation θ 150°C. To calculate the maximum power dissipation JMAX θ from Table 22, pick an appropriate T JA θ JA Table 22: Package Thermal Characteristics θ (º C/W) @ various flow rates (m/sec) ...
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... Figure 30: Voltage Factor vs. Supply Voltage Voltage Factor vs. Supply Voltage 2.25 2.3 2.35 2.4 2.45 2.5 Supply Voltage (V) Figure 31: Temperature Factor vs. Operating Temperature Temperature Factor vs. Operating Temperature -40 - Junction Temperature C 2.55 2.6 2.65 2.7 2. © 2007 QuickLogic Corporation ...
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... OUTP exhibits the power consumption in an Eclipse device. The chip was filled with (300) 8-bit counters Figure 32 (approximately 76% logic cell utilization). 2.5 2 1 © 2007 QuickLogic Corporation η η + 0.0948 + 0.01 LC CKBF CLBF η ] (mW) OUTP Figure 32: Power Consumption Power vs Freq. (Counter_300) ...
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... Figure 33: Power vs. Frequency (Absolute 50%, 70%, and 90% of the Available Resources on Chip learn more about power consumption, refer to Application Note 60 which is located at http://www.quicklogic.com/images/appnote60.pdf. • • 34 www.quicklogic.com • • • • Power vs. Frequency 50 100 150 Frequency (Mhz) 50% 70% 200 250 300 90% © 2007 QuickLogic Corporation ...
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... NOTE: Ramping the maximum voltage faster than 400 µs can cause the device to behave CC CCIO improperly. For users with a limited power budget, keep (V © 2007 QuickLogic Corporation - MAX V CC 400 us /V rails must take 400 µs or longer to reach the maximum value ...
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... TriState during CC, level signals. This pin must be connected to CCIO PLL can be connected to CC Table 11 for I differences when V CC Table 18 PLL (e.g GND not used. CC rail, not the V CC © 2007 QuickLogic Corporation is CCIO input CCIO PLL is CC for the . CCIO ...
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... V INREF<y> I/O bank does not require the use of INREF signal the pin should be connected to GND. NOTE: x -> number, y -> alphabetical character. © 2007 QuickLogic Corporation Figure 35: I/O Banks with Relevant Pins IO BANK A IO BANK B IO BANK F IO BANK E ...
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... Eclipse Family Data Sheet Rev. F QL6250 - 208 PQFP Pinout Diagram • • 38 www.quicklogic.com • • • • Eclipse QL6250-4PQ208C © 2007 QuickLogic Corporation ...
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... IO( IO( GND 75 34 VCCIO( IO( IO( IO( IO( IOCTRL( INREF( IOCTRL( IO(B) 84 © 2007 QuickLogic Corporation Table 25: 208 PQFP Pinout Table Function Pin Function IO(B) 85 IO(D) VCCIO(B) 86 VCC IO(B) 87 IO(D) VCC 88 IO(D) IO(B) 89 VCC IO(B) 90 IO(D) GND 91 IO(D) TDO 92 IOCTRL(D) PLLOUT(1) 93 INREF(D) GNDPLL(2) 94 IOCTRL(D) GND ...
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... Eclipse Family Data Sheet Rev. F QL6250 - 280 LFBGA Pinout Diagram Top QL6250-4PT280C Bottom • • 40 www.quicklogic.com • • • • Eclipse Pin A1 Corner © 2007 QuickLogic Corporation ...
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... GND C3 I/O(F) E12 VCC C4 I/O(F) E13 VCC C5 VCCIO(F) E14 GND C6 IOCTRL(F) E15 GND C7 I/O(F) E16 I/O(D) C8 I/O(F) E17 VCCIO(D) C9 VCCIO(F) E18 INREF(D) © 2007 QuickLogic Corporation Table 26: 280 LFBGA Pinout Table Ball Function Ball Function E19 IOCTRL(D) K16 I/O(C) F1 INREF(G) K17 I/O(D) F2 IOCTRL(G) K18 I/O(C) F3 I/O(G) K19 TRSTB F4 I/O(G) L1 I/O(H) F5 GND L2 ...
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... QL6250 - 484 PBGA Pinout Diagram Top QL6250-4PS484C Bottom • • 42 www.quicklogic.com • • • • Eclipse Pin A1 Pin A1 Corner © 2007 QuickLogic Corporation ...
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... B15 NC D15 IOCTRL(G) B16 I/O(G) D16 I/O(G) B17 I/O(G) D17 I/O(G) B18 I/O(G) D18 I/O(F) B19 PLLRST(0) D19 VCCPLL(0) B20 I/O(F) D20 I/O(F) B21 I/O(F) D21 I/O(F) B22 I/O(F) D22 I/O(F) © 2007 QuickLogic Corporation Table 27: 484 PBGA Pinout Table Ball Function Ball Function E1 IOCTRL( I/O( I/O(A) G3 I/O(A) E4 I/O(A) G4 I/O( I/O(A) E6 I/O(H) G6 I/O( ...
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... Y20 PLLRST(1) AB13 I/O(C) Y21 I/O(E) AB14 NC Y22 I/O(E) AB15 NC AA1 TDO AB16 NC AA2 PLLOUT(1) AB17 NC AA3 GND AB18 I/O(C) AA4 I/O(B) AB19 NC AA5 I/O(C) AB20 I/O(D) AA6 I/O(C) AB21 NC AA7 NC AB22 I/O(D) AA8 INREF(C) NC AA9 NC © 2007 QuickLogic Corporation Function I/O(C) I/O(C) I/O(D) I/O(D) I/O(D) I/O( I/O(D) I/O(E) GNDPLL(1) I/O(E) I/O(E) I/O(B) GNDPLL(2) PLLRST(2) I/O(B) I/O(B) I/O(C) I/O(C) IOCTRL(C) I/O(C) I/O(C) NC I/O(D) I/O(D) NC I/O(D) IOCTRL(D) I/O(D) I/O(D) I/O(E) GND VCCPLL(1) I/O(E) ...
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... QL6325 - 208 PQFP Pinout Diagram © 2007 QuickLogic Corporation Eclipse QL6325-4PQ208C Eclipse Family Data Sheet Rev. F www.quicklogic.com • • 45 • • • • ...
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... Eclipse Family Data Sheet Rev. F QL6325 - 208 PQFP Pinout Table Pin Function 1 PLLRST(3) 2 VCCPLL(3) 3 GND 4 GND 5 IO(A) 6 IO(A) 7 IO(A) 8 VCCIO(A) 9 IO(A) 10 IO(A) 11 IOCTRL(A) 12 VCC 13 INREF(A) 14 IOCTRL(A) 15 IO(A) 16 IO(A) 17 IO(A) 18 IO(A) 19 VCCIO(A) 20 IO(A) 21 GND 22 IO(A) 23 TDI 24 CLK(0) 25 CLK(1) 26 VCC 27 CLK(2)/PLLIN(2) 28 CLK(3)/PLLIN(1) 29 VCC CLK(4)/ 30 DEDCLK/PLLIN(0) ...
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... QL6325 - 280 LFBGA Pinout Diagram Top Eclipse QL6325-4PT280C Bottom © 2007 QuickLogic Corporation Eclipse Family Data Sheet Rev. F Pin A1 Corner • • www.quicklogic.com 47 • • • • ...
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... Eclipse Family Data Sheet Rev. F QL6325 - 280 LFBGA Pinout Table Ball Function Ball A1 PLLOUT(3) C10 A2 GNDPLL(0) C11 A3 I/O(F) C12 A4 I/O(F) C13 A5 I/O(F) C14 A6 IOCTRL(F) C15 A7 I/O(F) C16 A8 I/O(F) C17 A9 I/O(F) C18 A10 CLK(7) C19 A11 I/O(E) D1 A12 I/O(E) D2 A13 I/O(E) D3 A14 IOCTRL(E) D4 A15 I/O(E) D5 A16 I/O(E) D6 A17 I/O(E) D7 A18 PLLRST(1) D8 A19 GND D9 B1 ...
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... QL6325 - 484 PBGA Pinout Diagram Top Eclipse QL6325-4PS484C Bottom © 2007 QuickLogic Corporation Eclipse Family Data Sheet Rev. F Pin A1 Pin A1 Corner www ...
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... Eclipse Family Data Sheet Rev. F QL6325 - 484 PBGA Pinout Table Ball Function Ball A1 I/O( PLLRST( I/O( I/O( I/O( I/O( I/O( IOCTRL( I/O(H) C9 A10 NC C10 A11 NC C11 A12 TCK C12 A13 I/O(G) C13 A14 I/O(G) C14 A15 I/O(G) C15 A16 I/O(G) C16 A17 I/O(G) C17 A18 ...
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... I/O(E) P7 I/O(B) R22 I/O(E) P8 VCC T1 I/O(B) P9 GND T2 I/O(B) P10 VCC T3 I/O(B) P11 GND T4 I/O(B) P12 VCC T5 I/O(B) P13 VCC T6 VCCIO(B) P14 GND T7 GND P15 VDED T8 I/O(C) © 2007 QuickLogic Corporation Ball Function Ball Function I/O(B) T10 TRSTB V3 I/O(B) T11 GND V4 I/O(B) T12 NC V5 I/O(B) T13 I/O(D) V6 I/O(C) T14 NC V7 I/O(C) T15 I/O(D) V8 I/O(C) T16 GND V9 NC ...
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... Eclipse Family Data Sheet Rev. F QL6500 - 280 LFBGA Pinout Diagram Top QL6500-4PT280C Bottom • • 52 www.quicklogic.com • • • • Eclipse Pin A1 Corner © 2007 QuickLogic Corporation ...
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... GND C3 I/O(F) E12 VCC C4 I/O(F) E13 VCC C5 VCCIO(F) E14 GND C6 IOCTRL(F) E15 GND C7 I/O(F) E16 I/O(D) C8 I/O(F) E17 VCCIO(D) C9 VCCIO(F) E18 INREF(D) © 2007 QuickLogic Corporation Table 31: 280 LFBGA Pinout Table Ball Function Ball Function E19 IOCTRL(D) K16 I/O(C) F1 INREF(G) K17 I/O(D) F2 IOCTRL(G) K18 I/O(C) F3 I/O(G) K19 TRSTB F4 I/O(G) L1 I/O(H) F5 GND L2 ...
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... QL6500 - 484 PBGA Pinout Diagram Top QL6500-4PS484C Bottom • • 54 www.quicklogic.com • • • • Eclipse Pin A1 Pin A1 Corner © 2007 QuickLogic Corporation ...
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... D14 I/O(G) B15 I/O(G) D15 IOCTRL(G) B16 I/O(G) D16 I/O(G) B17 I/O(G) D17 I/O(G) B18 I/O(G) D18 I/O(F) B19 PLLRST(0) D19 VCCPLL(0) B20 I/O(F) D20 I/O(F) B21 I/O(F) D21 I/O(F) B22 I/O(F) D22 I/O(F) © 2007 QuickLogic Corporation Table 32: 484 PBGA Pinout Table Ball Function Ball Function E1 IOCTRL(A) G1 I/O(A) E2 I/O(A) G2 I/O(A) E3 I/O(A) G3 I/O(A) E4 I/O(A) G4 I/O(A) E5 I/O(A) G5 I/O(A) E6 I/O(H) G6 I/O(A) E7 I/O(H) G7 GND ...
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... PLLOUT(0) AB12 I/O(B) Y20 PLLRST(1) AB13 I/O(C) Y21 I/O(E) AB14 I/O(C) Y22 I/O(E) AB15 I/O(C) AA1 TDO AB16 I/O(C) AA2 PLLOUT(1) AB17 I/O(C) AA3 GND AB18 I/O(C) AA4 I/O(B) AB19 I/O(D) AA5 I/O(C) AB20 I/O(D) AA6 I/O(C) AB21 I/O(D) AA7 I/O(C) AB22 I/O(D) AA8 INREF(C) I/O(D) AA9 I/O(C) © 2007 QuickLogic Corporation Function I/O(C) I/O(C) I/O(D) I/O(D) I/O(D) I/O(D) I/O(D) I/O(D) I/O(D) I/O(E) GNDPLL(1) I/O(E) I/O(E) I/O(B) GNDPLL(2) PLLRST(2) I/O(B) I/O(B) I/O(C) I/O(C) IOCTRL(C) I/O(C) I/O(C) I/O(C) I/O(D) I/O(D) I/O(D) I/O(D) IOCTRL(D) I/O(D) I/O(D) I/O(E) GND VCCPLL(1) I/O(E) ...
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... QL6500 - 516 PBGA Pinout Diagram Top Eclipse QL6500-4PB516C Bottom © 2007 QuickLogic Corporation Eclipse Family Data Sheet Rev. F PIN A1 CORNER www.quicklogic.com • • 57 • • • • ...
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... GND N15 GND I/O(D) N16 GND I/O(D) N21 GND I/O(D) N22 I/O(D) I/O(D) N23 I/O(D) I/O(D) N24 I/O(D) I/O(G) N25 I/O(D) I/O(G) N26 I/O(D) I/O(G) P1 I/O(H) I/O(G) P2 I/O(H) © 2007 QuickLogic Corporation Ball Function P3 I/O(H) P4 VCC P5 I/O(H) P6 VCCIO(H) P11 GND P12 GND P13 GND P14 GND P15 GND P16 GND P21 VCCIO(C) P22 I/O(C) P23 VCC P24 ...
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... VCC W6 VCC AA16 VCC W21 VCC AA17 GND W22 I/O(C) AA18 VCCIO(B) W23 I/O(C) AA19 VCC W24 I/O(C) AA20 VCCIO(B) © 2007 QuickLogic Corporation Table 33: 516 PBGA Pinout Table (Continued) Ball Function Ball Function AA21 GND AC3 I/O(A) AA22 VCCPLL(2) AC4 I/O(A) AA23 I/O(C) AC5 I/O(A) AA24 I/O(C) AC6 ...
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... Eclipse Family Data Sheet Rev. F QL6600 - 280 LFBGA Pinout Diagram Top QL6600-4PT280C Bottom • • 60 www.quicklogic.com • • • • Eclipse Pin A1 Corner © 2007 QuickLogic Corporation ...
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... GND C3 I/O(F) E12 VCC C4 I/O(F) E13 VCC C5 VCCIO(F) E14 GND C6 IOCTRL(F) E15 GND C7 I/O(F) E16 I/O(D) C8 I/O(F) E17 VCCIO(D) C9 VCCIO(F) E18 INREF(D) © 2007 QuickLogic Corporation Table 34: 280 LFBGA Pinout Table Ball Function Ball Function E19 IOCTRL(D) K16 I/O(C) F1 INREF(G) K17 I/O(D) F2 IOCTRL(G) K18 I/O(C) F3 I/O(G) K19 TRSTB F4 I/O(G) L1 I/O(H) F5 GND L2 ...
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... QL6600 - 484 PBGA Pinout Diagram Top QL6600-4PS484C Bottom • • 62 www.quicklogic.com • • • • Eclipse Pin A1 Pin A1 Corner © 2007 QuickLogic Corporation ...
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... D14 I/O(G) B15 I/O(G) D15 IOCTRL(G) B16 I/O(G) D16 I/O(G) B17 I/O(G) D17 I/O(G) B18 I/O(G) D18 I/O(F) B19 PLLRST(0) D19 VCCPLL(0) B20 I/O(F) D20 I/O(F) B21 I/O(F) D21 I/O(F) B22 I/O(F) D22 I/O(F) © 2007 QuickLogic Corporation Table 35: 484 PBGA Pinout Table Ball Function Ball Function E1 IOCTRL(A) G1 I/O(A) E2 I/O(A) G2 I/O(A) E3 I/O(A) G3 I/O(A) E4 I/O(A) G4 I/O(A) E5 I/O(A) G5 I/O(A) E6 I/O(H) G6 I/O(A) E7 I/O(H) G7 GND ...
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... PLLOUT(0) AB12 I/O(B) Y20 PLLRST(1) AB13 I/O(C) Y21 I/O(E) AB14 I/O(C) Y22 I/O(E) AB15 I/O(C) AA1 TDO AB16 I/O(C) AA2 PLLOUT(1) AB17 I/O(C) AA3 GND AB18 I/O(C) AA4 I/O(B) AB19 I/O(D) AA5 I/O(C) AB20 I/O(D) AA6 I/O(C) AB21 I/O(D) AA7 I/O(C) AB22 I/O(D) AA8 INREF(C) I/O(D) AA9 I/O(C) © 2007 QuickLogic Corporation Function I/O(C) I/O(C) I/O(D) I/O(D) I/O(D) I/O(D) I/O(D) I/O(D) I/O(D) I/O(E) GNDPLL(1) I/O(E) I/O(E) I/O(B) GNDPLL(2) PLLRST(2) I/O(B) I/O(B) I/O(C) I/O(C) IOCTRL(C) I/O(C) I/O(C) I/O(C) I/O(D) I/O(D) I/O(D) I/O(D) IOCTRL(D) I/O(D) I/O(D) I/O(E) GND VCCPLL(1) I/O(E) ...
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... QL6600 - 516 PBGA Pinout Diagram Top Eclipse QL6600-4PB516C Bottom © 2007 QuickLogic Corporation Eclipse Family Data Sheet Rev. F PIN A1 CORNER www.quicklogic.com • • 65 • • • • ...
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... GND N15 GND I/O(D) N16 GND I/O(D) N21 GND I/O(D) N22 I/O(D) I/O(D) N23 I/O(D) I/O(D) N24 I/O(D) I/O(G) N25 I/O(D) I/O(G) N26 I/O(D) I/O(G) P1 I/O(H) I/O(G) P2 I/O(H) © 2007 QuickLogic Corporation Ball Function P3 I/O(H) P4 VCC P5 I/O(H) P6 VCCIO(H) P11 GND P12 GND P13 GND P14 GND P15 GND P16 GND P21 VCCIO(C) P22 I/O(C) P23 VCC P24 ...
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... VCC W6 VCC AA16 VCC W21 VCC AA17 GND W22 I/O(C) AA18 VCCIO(B) W23 I/O(C) AA19 VCC W24 I/O(C) AA20 VCCIO(B) © 2007 QuickLogic Corporation Table 36: 516 PBGA Pinout Table (Continued) Ball Function Ball Function AA21 GND AC3 I/O(A) AA22 VCCPLL(2) AC4 I/O(A) AA23 I/O(C) AC5 I/O(A) AA24 I/O(C) AC6 ...
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... Eclipse Family Data Sheet Rev. F Package Mechanical Drawings 208 PQFP Packaging Drawing • • 68 www.quicklogic.com • • • • © 2007 QuickLogic Corporation ...
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... LFBGA Packaging Drawing © 2007 QuickLogic Corporation Eclipse Family Data Sheet Rev. F www.quicklogic.com • • 69 • • • • ...
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... Eclipse Family Data Sheet Rev. F 484 PBGA Packaging Drawing • • 70 www.quicklogic.com • • • • © 2007 QuickLogic Corporation ...
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... PBGA Packaging Drawing © 2007 QuickLogic Corporation Eclipse Family Data Sheet Rev. F www.quicklogic.com • • 71 • • • • ...
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... E-mail: info@quicklogic.com Sales: www.quicklogic.com/sales Support: www.quicklogic.com/support Internet: www.quicklogic.com • • 72 www.quicklogic.com • • • • Table 37: Packaging Options QL6250 and QL6325 Pin/Ball Pitch 208 PQFP 0. 280 LFBGA 0.80 mm 484 PBGA 1 6250 - 7 PQ208 C Operating Range C = Commercial I = Industrial M = Military Package PQ208 PT280 ...
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... Brian Faith and Kathleen Murchek Brian Faith and Kathleen Murchek Brian Faith, Mehul Kochar, and Kathleen Murchek Combined previous Eclipse Family data sheet with QL6250, QL6325, QL6500, and QL6600 data sheets to create one complete Eclipse Family Data Sheet. Jason Lew and Kathleen Murchek Changed pin G16 from VPUMP to GND in all PS484 pinout tables ...