ql6325-4pt280c QuickLogic Corp, ql6325-4pt280c Datasheet - Page 13

• Manufacturer Part Number: ql6325-4pt280c
• Description: Combining Performance, Density, And Embedded Ram
• Manufacturer: QuickLogic Corp

Quad-Net Network
There are five Quad-Net local clock networks in each quadrant for a total of 20 in a device. Each Quad-Net is
local to a quadrant. Before driving the columns clock buffers, the quad-net is driven by the output of a mux
which selects between the CLK input and an internally generated clock source (see
Dedicated Clock
There is one dedicated clock each device of the Eclipse Family (QL6250, QL6325, QL6500, and QL6600).
This clock connects to the clock input of the Logic Cell and I/O registers, and RAM blocks through a hardwired
connection and is multiplexed with the programmable clock input. The dedicated clock provides a fast global
network with low skew. Users have the ability to select either the dedicated clock or the programmable clock
(Figure
NOTE:
Application Note 68 at http://www.quicklogic.com/images/appnote68.pdf.
I/O Control and Local Hi-Drives
Each bank of I/Os has two input-only pins that can be programmed to drive the RST, CLK and EN inputs of
I/Os in that bank. These input only pins also serve as high drive inputs to a quadrant. As an I/O control or
high drive, these buffers can be driven by the internal logic. I/O control pins, called IOCTRL in the pin tables,
are 2.5 V, LVCMOS2, compliant.
© 2007 QuickLogic Corporation
Global Clock
(CLK) Input
For more information on the clocking capabilities of Eclipse FPGAs, refer to the QuickLogic
11). The dedicated clock is 2.5 V, LVCMOS2, compliant.
Internally generated clock, or
clock from general routing network
Programmable Clock or
General Routing
Figure 11: Dedicated Clock Circuitry within Logic Cell
Figure 10: Global Clock Structure Schematic
Dedicated Clock
t PGCK
Global Clock Buffer
Global Clock Network
CLK
t BGCK
Eclipse Family Data Sheet Rev. F
Figure
FF
10).
www.quicklogic.com
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