ql6325-4pt280c QuickLogic Corp, ql6325-4pt280c Datasheet - Page 7

• Manufacturer Part Number: ql6325-4pt280c
• Description: Combining Performance, Density, And Embedded Ram
• Manufacturer: QuickLogic Corp

a. Because PLLCLK_IN and PLLRST signals have INPAD, and PLLPAD_OUT has OUTPAD, you do not have to add additional pads
PLL Signals
Table 5
NOTE:
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LOCK_DETECT
ONn_OFFCHIP
CLKNET_OUT
to your design.
PLLCLK_OUT
PLLPAD_OUT
Signal Name
PLLCLK_IN
PLLRST
For PLL AC specifications, contact the factory.
summarizes the key signals in QuickLogic PLLs.
a
Input clock signal
Active High Reset
This signal must be asserted and then released in order for the LOCK_DETECT to work.
PLL output
chip. This is a static signal, not a dynamic signal.
Tied to GND = outgoing signal drives internal gates.
Tied to VCC = outgoing signal used off-chip.
Out to internal gates
this signal cannot be used in the same quadrant where the PLL signal is used (PLLCLK_OUT).
Out from PLL to internal gates
For this to work, ONn_OFFCHIP must be tied to GND.
Out to off-chip
be tied to VCC.
Active High Lock detection signal
10 clock cycles. However, it can take a maximum of 200 clock cycles to sync with the input clock
upon release of the RESET signal.
This signal selects whether the PLL will drive the internal clock network or be used off-
This outgoing signal is used off-chip. For this to work, ONn_OFFCHIP signal must
If PLLRST is asserted, then CLKNET_OUT and PLLPAD_OUT are reset to 0.
This signal bypasses the PLL logic before driving the internal gates. Note that
Table 5: PLL Signals
This signal can drive the internal gates after going through the PLL.
NOTE: For simulation purposes, this signal gets asserted after
Description
Eclipse Family Data Sheet Rev. F
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